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Commit dae430c6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'amd64-edac-updates-for-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp 

Pull AMD64 EDAC fixes from Borislav Petkov:
 "A bunch of fixes/updates for the AMD side of EDAC including

   * MCE decoding updates
   * tree-wide EDAC sweep making pci_device_ids __devinitconst
   * Scrub rate API correction
   * two amd64_edac corrections for K8 boxes and sysfs csrow nodes"

* tag 'amd64-edac-updates-for-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
  MCE, AMD: Constify error tables
  MCE, AMD: Correct bank 5 error signatures
  MCE, AMD: Rework NB MCE signatures
  MCE, AMD: Correct VB data error description
  MCE, AMD: Correct ucode patch buffer description
  MCE, AMD: Correct some MC0 error types
  EDAC: Make pci_device_id tables __devinitconst.
  EDAC: Correct scrub rate API
  amd64_edac: Fix K8 revD and later chip select sizes
  amd64_edac: Fix missing csrows sysfs nodes
parents cf821923 ebe2aea8

Documentation/edac.txt

+2 −2
Original line number Diff line number Diff line
@@ -334,8 +334,8 @@ Sdram memory scrubbing rate: 


	Reading the file will return the actual scrubbing rate employed.



	If configuration fails or memory scrubbing is not implemented, the value

	of the attribute file will be -1.

	If configuration fails or memory scrubbing is not implemented, accessing

	that attribute will fail.

drivers/edac/amd64_edac.c

+36 −14
Original line number Diff line number Diff line
@@ -1132,12 +1132,36 @@ static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, 
		return ddr2_cs_size(cs_mode, dclr & WIDTH_128);

	}

	else if (pvt->ext_model >= K8_REV_D) {

		unsigned diff;

		WARN_ON(cs_mode > 10);



		if (cs_mode == 3 || cs_mode == 8)

			return 32 << (cs_mode - 1);

		else

			return 32 << cs_mode;

		/*

		 * the below calculation, besides trying to win an obfuscated C

		 * contest, maps cs_mode values to DIMM chip select sizes. The

		 * mappings are:

		 *

		 * cs_mode	CS size (mb)

		 * =======	============

		 * 0		32

		 * 1		64

		 * 2		128

		 * 3		128

		 * 4		256

		 * 5		512

		 * 6		256

		 * 7		512

		 * 8		1024

		 * 9		1024

		 * 10		2048

		 *

		 * Basically, it calculates a value with which to shift the

		 * smallest CS size of 32MB.

		 *

		 * ddr[23]_cs_size have a similar purpose.

		 */

		diff = cs_mode/3 + (unsigned)(cs_mode > 5);



		return 32 << (cs_mode - diff);

	}

	else {

		WARN_ON(cs_mode > 6);
@@ -2133,6 +2157,7 @@ static void read_mc_regs(struct amd64_pvt *pvt) 
static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)

{

	u32 cs_mode, nr_pages;

	u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;



	/*

	 * The math on this doesn't look right on the surface because x/2*4 can
@@ -2141,16 +2166,10 @@ static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) 
	 * number of bits to shift the DBAM register to extract the proper CSROW

	 * field.

	 */

	cs_mode = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF;

	cs_mode =  (dbam >> ((csrow_nr / 2) * 4)) & 0xF;



	nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);



	/*

	 * If dual channel then double the memory size of single channel.

	 * Channel count is 1 or 2

	 */

	nr_pages <<= (pvt->channel_count - 1);



	debugf0("  (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode);

	debugf0("    nr_pages= %u  channel-count = %d\n",

		nr_pages, pvt->channel_count);
@@ -2181,7 +2200,7 @@ static int init_csrows(struct mem_ctl_info *mci) 
	for_each_chip_select(i, 0, pvt) {

		csrow = &mci->csrows[i];



		if (!csrow_enabled(i, 0, pvt)) {

		if (!csrow_enabled(i, 0, pvt) && !csrow_enabled(i, 1, pvt)) {

			debugf1("----CSROW %d EMPTY for node %d\n", i,

				pvt->mc_node_id);

			continue;
@@ -2191,7 +2210,10 @@ static int init_csrows(struct mem_ctl_info *mci) 
			i, pvt->mc_node_id);



		empty = 0;

		if (csrow_enabled(i, 0, pvt))

			csrow->nr_pages = amd64_csrow_nr_pages(pvt, 0, i);

		if (csrow_enabled(i, 1, pvt))

			csrow->nr_pages += amd64_csrow_nr_pages(pvt, 1, i);

		find_csrow_limits(mci, i, &input_addr_min, &input_addr_max);

		sys_addr = input_addr_to_sys_addr(mci, input_addr_min);

		csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT);
@@ -2685,7 +2707,7 @@ static void __devexit amd64_remove_one_instance(struct pci_dev *pdev) 
 * PCI core identifies what devices are on a system during boot, and then

 * inquiry this table to see if this driver is for a given device found.

 */

static const struct pci_device_id amd64_pci_table[] __devinitdata = {

static DEFINE_PCI_DEVICE_TABLE(amd64_pci_table) = {

	{

		.vendor		= PCI_VENDOR_ID_AMD,

		.device		= PCI_DEVICE_ID_AMD_K8_NB_MEMCTL,

drivers/edac/amd76x_edac.c

+1 −1
Original line number Diff line number Diff line
@@ -321,7 +321,7 @@ static void __devexit amd76x_remove_one(struct pci_dev *pdev) 
	edac_mc_free(mci);

}



static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {

static DEFINE_PCI_DEVICE_TABLE(amd76x_pci_tbl) = {

	{

	 PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,

	 AMD762},

drivers/edac/e752x_edac.c

+1 −1
Original line number Diff line number Diff line
@@ -1380,7 +1380,7 @@ static void __devexit e752x_remove_one(struct pci_dev *pdev) 
	edac_mc_free(mci);

}



static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {

static DEFINE_PCI_DEVICE_TABLE(e752x_pci_tbl) = {

	{

	 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,

	 E7520},

drivers/edac/e7xxx_edac.c

+1 −1
Original line number Diff line number Diff line
@@ -525,7 +525,7 @@ static void __devexit e7xxx_remove_one(struct pci_dev *pdev) 
	edac_mc_free(mci);

}



static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {

static DEFINE_PCI_DEVICE_TABLE(e7xxx_pci_tbl) = {

	{

	 PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,

	 E7205},