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Commit da52faa5 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge branch 'pinmux/next/pin-no-gpio' of git://linuxtv.org/pinchartl/fbdev into devel 



Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents f29bdca0 4f82e3ee

drivers/pinctrl/sh-pfc/core.c

+76 −23
Original line number Diff line number Diff line
@@ -82,24 +82,20 @@ int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) 
	unsigned int offset;

	unsigned int i;



	if (pfc->info->ranges == NULL)

		return pin;



	for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {

		const struct pinmux_range *range = &pfc->info->ranges[i];

	for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {

		const struct sh_pfc_pin_range *range = &pfc->ranges[i];



		if (pin <= range->end)

			return pin >= range->begin

			     ? offset + pin - range->begin : -1;

			return pin >= range->start

			     ? offset + pin - range->start : -1;



		offset += range->end - range->begin + 1;

		offset += range->end - range->start + 1;

	}



	return -EINVAL;

}



static int sh_pfc_enum_in_range(pinmux_enum_t enum_id,

				const struct pinmux_range *r)

static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)

{

	if (enum_id < r->begin)

		return 0;
@@ -194,7 +190,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, 
	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);

}



static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,

static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,

				 const struct pinmux_cfg_reg **crp, int *fieldp,

				 int *valuep)

{
@@ -238,10 +234,10 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, 
	return -EINVAL;

}



static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,

			      pinmux_enum_t *enum_idp)

static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,

			      u16 *enum_idp)

{

	const pinmux_enum_t *data = pfc->info->gpio_data;

	const u16 *data = pfc->info->gpio_data;

	int k;



	if (pos) {
@@ -264,7 +260,7 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos, 
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)

{

	const struct pinmux_cfg_reg *cr = NULL;

	pinmux_enum_t enum_id;

	u16 enum_id;

	const struct pinmux_range *range;

	int in_range, pos, field, value;

	int ret;
@@ -283,14 +279,6 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) 
		range = &pfc->info->input;

		break;



	case PINMUX_TYPE_INPUT_PULLUP:

		range = &pfc->info->input_pu;

		break;



	case PINMUX_TYPE_INPUT_PULLDOWN:

		range = &pfc->info->input_pd;

		break;



	default:

		return -EINVAL;

	}
@@ -350,6 +338,67 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) 
	return 0;

}



static int sh_pfc_init_ranges(struct sh_pfc *pfc)

{

	struct sh_pfc_pin_range *range;

	unsigned int nr_ranges;

	unsigned int i;



	if (pfc->info->pins[0].pin == (u16)-1) {

		/* Pin number -1 denotes that the SoC doesn't report pin numbers

		 * in its pin arrays yet. Consider the pin numbers range as

		 * continuous and allocate a single range.

		 */

		pfc->nr_ranges = 1;

		pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),

					   GFP_KERNEL);

		if (pfc->ranges == NULL)

			return -ENOMEM;



		pfc->ranges->start = 0;

		pfc->ranges->end = pfc->info->nr_pins - 1;

		pfc->nr_gpio_pins = pfc->info->nr_pins;



		return 0;

	}



	/* Count, allocate and fill the ranges. The PFC SoC data pins array must

	 * be sorted by pin numbers, and pins without a GPIO port must come

	 * last.

	 */

	for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {

		if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)

			nr_ranges++;

	}



	pfc->nr_ranges = nr_ranges;

	pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,

				   GFP_KERNEL);

	if (pfc->ranges == NULL)

		return -ENOMEM;



	range = pfc->ranges;

	range->start = pfc->info->pins[0].pin;



	for (i = 1; i < pfc->info->nr_pins; ++i) {

		if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)

			continue;



		range->end = pfc->info->pins[i-1].pin;

		if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))

			pfc->nr_gpio_pins = range->end + 1;



		range++;

		range->start = pfc->info->pins[i].pin;

	}



	range->end = pfc->info->pins[i-1].pin;

	if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))

		pfc->nr_gpio_pins = range->end + 1;



	return 0;

}



#ifdef CONFIG_OF

static const struct of_device_id sh_pfc_of_table[] = {

#ifdef CONFIG_PINCTRL_PFC_R8A73A4
@@ -440,6 +489,10 @@ static int sh_pfc_probe(struct platform_device *pdev) 


	pinctrl_provide_dummies();



	ret = sh_pfc_init_ranges(pfc);

	if (ret < 0)

		return ret;



	/*

	 * Initialize pinctrl bindings first

	 */

drivers/pinctrl/sh-pfc/core.h

+9 −1
Original line number Diff line number Diff line
@@ -25,6 +25,11 @@ struct sh_pfc_window { 
struct sh_pfc_chip;

struct sh_pfc_pinctrl;



struct sh_pfc_pin_range {

	u16 start;

	u16 end;

};



struct sh_pfc {

	struct device *dev;

	const struct sh_pfc_soc_info *info;
@@ -34,7 +39,10 @@ struct sh_pfc { 
	unsigned int num_windows;

	struct sh_pfc_window *window;



	unsigned int nr_pins;

	struct sh_pfc_pin_range *ranges;

	unsigned int nr_ranges;



	unsigned int nr_gpio_pins;



	struct sh_pfc_chip *gpio;

	struct sh_pfc_chip *func;

drivers/pinctrl/sh-pfc/gpio.c

+19 −26
Original line number Diff line number Diff line
@@ -48,11 +48,11 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) 
	return gpio_to_pfc_chip(gc)->pfc;

}



static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio,

static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,

			      struct sh_pfc_gpio_data_reg **reg,

			      unsigned int *bit)

{

	int idx = sh_pfc_get_pin_index(chip->pfc, gpio);

	int idx = sh_pfc_get_pin_index(chip->pfc, offset);

	struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];



	*reg = &chip->regs[gpio_pin->dreg];
@@ -76,11 +76,11 @@ static void gpio_write_data_reg(struct sh_pfc_chip *chip, 
	sh_pfc_write_raw_reg(mem, dreg->reg_width, value);

}



static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)

static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)

{

	struct sh_pfc *pfc = chip->pfc;

	struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio];

	const struct sh_pfc_pin *pin = &pfc->info->pins[gpio];

	struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];

	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];

	const struct pinmux_data_reg *dreg;

	unsigned int bit;

	unsigned int i;
@@ -224,8 +224,8 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip) 
	struct gpio_chip *gc = &chip->gpio_chip;

	int ret;



	chip->pins = devm_kzalloc(pfc->dev, pfc->nr_pins * sizeof(*chip->pins),

				  GFP_KERNEL);

	chip->pins = devm_kzalloc(pfc->dev, pfc->info->nr_pins *

				  sizeof(*chip->pins), GFP_KERNEL);

	if (chip->pins == NULL)

		return -ENOMEM;
@@ -245,7 +245,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip) 
	gc->dev = pfc->dev;

	gc->owner = THIS_MODULE;

	gc->base = 0;

	gc->ngpio = pfc->nr_pins;

	gc->ngpio = pfc->nr_gpio_pins;



	return 0;

}
@@ -293,7 +293,7 @@ static int gpio_function_setup(struct sh_pfc_chip *chip) 


	gc->label = pfc->info->name;

	gc->owner = THIS_MODULE;

	gc->base = pfc->nr_pins;

	gc->base = pfc->nr_gpio_pins;

	gc->ngpio = pfc->info->nr_func_gpios;



	return 0;
@@ -334,10 +334,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *), 


int sh_pfc_register_gpiochip(struct sh_pfc *pfc)

{

	const struct pinmux_range *ranges;

	struct pinmux_range def_range;

	struct sh_pfc_chip *chip;

	unsigned int nr_ranges;

	unsigned int i;

	int ret;
@@ -367,24 +364,20 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc) 


	pfc->gpio = chip;



	/* Register the GPIO to pin mappings. */

	if (pfc->info->ranges == NULL) {

		def_range.begin = 0;

		def_range.end = pfc->info->nr_pins - 1;

		ranges = &def_range;

		nr_ranges = 1;

	} else {

		ranges = pfc->info->ranges;

		nr_ranges = pfc->info->nr_ranges;

	}

	/* Register the GPIO to pin mappings. As pins with GPIO ports must come

	 * first in the ranges, skip the pins without GPIO ports by stopping at

	 * the first range that contains such a pin.

	 */

	for (i = 0; i < pfc->nr_ranges; ++i) {

		const struct sh_pfc_pin_range *range = &pfc->ranges[i];



	for (i = 0; i < nr_ranges; ++i) {

		const struct pinmux_range *range = &ranges[i];

		if (range->start >= pfc->nr_gpio_pins)

			break;



		ret = gpiochip_add_pin_range(&chip->gpio_chip,

					     dev_name(pfc->dev),

					     range->begin, range->begin,

					     range->end - range->begin + 1);

					     range->start, range->start,

					     range->end - range->start + 1);

		if (ret < 0)

			return ret;

	}

drivers/pinctrl/sh-pfc/pfc-r8a73a4.c

+65 −92
Original line number Diff line number Diff line
@@ -28,78 +28,78 @@ 


#define CPU_ALL_PORT(fn, pfx, sfx)					\

	/*  Port0 - Port30 */						\

	PORT_10(fn, pfx, sfx),						\

	PORT_10(fn, pfx##1, sfx),					\

	PORT_10(fn, pfx##2, sfx),					\

	PORT_1(fn,  pfx##30, sfx),					\

	PORT_10(0, fn, pfx, sfx),					\

	PORT_10(10, fn, pfx##1, sfx),					\

	PORT_10(20, fn, pfx##2, sfx),					\

	PORT_1(30, fn, pfx##30, sfx),					\

	/* Port32 - Port40 */						\

	PORT_1(fn,  pfx##32, sfx),	PORT_1(fn,  pfx##33, sfx),	\

	PORT_1(fn,  pfx##34, sfx),	PORT_1(fn,  pfx##35, sfx),	\

	PORT_1(fn,  pfx##36, sfx),	PORT_1(fn,  pfx##37, sfx),	\

	PORT_1(fn,  pfx##38, sfx),	PORT_1(fn,  pfx##39, sfx),	\

	PORT_1(fn,  pfx##40, sfx),					\

	PORT_1(32, fn, pfx##32, sfx),	PORT_1(33, fn, pfx##33, sfx),	\

	PORT_1(34, fn, pfx##34, sfx),	PORT_1(35, fn, pfx##35, sfx),	\

	PORT_1(36, fn, pfx##36, sfx),	PORT_1(37, fn, pfx##37, sfx),	\

	PORT_1(38, fn, pfx##38, sfx),	PORT_1(39, fn, pfx##39, sfx),	\

	PORT_1(40, fn, pfx##40, sfx),					\

	/* Port64  - Port85 */						\

	PORT_1(fn, pfx##64, sfx),	PORT_1(fn, pfx##65, sfx),	\

	PORT_1(fn, pfx##66, sfx),	PORT_1(fn, pfx##67, sfx),	\

	PORT_1(fn, pfx##68, sfx),	PORT_1(fn, pfx##69, sfx),	\

	PORT_10(fn, pfx##7, sfx),					\

	PORT_1(fn, pfx##80, sfx),	PORT_1(fn, pfx##81, sfx),	\

	PORT_1(fn, pfx##82, sfx),	PORT_1(fn, pfx##83, sfx),	\

	PORT_1(fn, pfx##84, sfx),	PORT_1(fn, pfx##85, sfx),	\

	PORT_1(64, fn, pfx##64, sfx),	PORT_1(65, fn, pfx##65, sfx),	\

	PORT_1(66, fn, pfx##66, sfx),	PORT_1(67, fn, pfx##67, sfx),	\

	PORT_1(68, fn, pfx##68, sfx),	PORT_1(69, fn, pfx##69, sfx),	\

	PORT_10(70, fn, pfx##7, sfx),					\

	PORT_1(80, fn, pfx##80, sfx),	PORT_1(81, fn, pfx##81, sfx),	\

	PORT_1(82, fn, pfx##82, sfx),	PORT_1(83, fn, pfx##83, sfx),	\

	PORT_1(84, fn, pfx##84, sfx),	PORT_1(85, fn, pfx##85, sfx),	\

	/* Port96  - Port126 */						\

	PORT_1(fn, pfx##96, sfx),	PORT_1(fn, pfx##97, sfx),	\

	PORT_1(fn, pfx##98, sfx),	PORT_1(fn, pfx##99, sfx),	\

	PORT_10(fn, pfx##10, sfx),					\

	PORT_10(fn, pfx##11, sfx),					\

	PORT_1(fn, pfx##120, sfx),	PORT_1(fn, pfx##121, sfx),	\

	PORT_1(fn, pfx##122, sfx),	PORT_1(fn, pfx##123, sfx),	\

	PORT_1(fn, pfx##124, sfx),	PORT_1(fn, pfx##125, sfx),	\

	PORT_1(fn, pfx##126, sfx),					\

	PORT_1(96, fn, pfx##96, sfx),	PORT_1(97, fn, pfx##97, sfx),	\

	PORT_1(98, fn, pfx##98, sfx),	PORT_1(99, fn, pfx##99, sfx),	\

	PORT_10(100, fn, pfx##10, sfx),					\

	PORT_10(110, fn, pfx##11, sfx),					\

	PORT_1(120, fn, pfx##120, sfx),	PORT_1(121, fn, pfx##121, sfx),	\

	PORT_1(122, fn, pfx##122, sfx),	PORT_1(123, fn, pfx##123, sfx),	\

	PORT_1(124, fn, pfx##124, sfx),	PORT_1(125, fn, pfx##125, sfx),	\

	PORT_1(126, fn, pfx##126, sfx),					\

	/* Port128 - Port134 */						\

	PORT_1(fn, pfx##128, sfx),	PORT_1(fn, pfx##129, sfx),	\

	PORT_1(fn, pfx##130, sfx),	PORT_1(fn, pfx##131, sfx),	\

	PORT_1(fn, pfx##132, sfx),	PORT_1(fn, pfx##133, sfx),	\

	PORT_1(fn, pfx##134, sfx),					\

	PORT_1(128, fn, pfx##128, sfx),	PORT_1(129, fn, pfx##129, sfx),	\

	PORT_1(130, fn, pfx##130, sfx),	PORT_1(131, fn, pfx##131, sfx),	\

	PORT_1(132, fn, pfx##132, sfx),	PORT_1(133, fn, pfx##133, sfx),	\

	PORT_1(134, fn, pfx##134, sfx),					\

	/* Port160 - Port178 */						\

	PORT_10(fn, pfx##16, sfx),					\

	PORT_1(fn, pfx##170, sfx),	PORT_1(fn, pfx##171, sfx),	\

	PORT_1(fn, pfx##172, sfx),	PORT_1(fn, pfx##173, sfx),	\

	PORT_1(fn, pfx##174, sfx),	PORT_1(fn, pfx##175, sfx),	\

	PORT_1(fn, pfx##176, sfx),	PORT_1(fn, pfx##177, sfx),	\

	PORT_1(fn, pfx##178, sfx),					\

	PORT_10(160, fn, pfx##16, sfx),					\

	PORT_1(170, fn, pfx##170, sfx),	PORT_1(171, fn, pfx##171, sfx),	\

	PORT_1(172, fn, pfx##172, sfx),	PORT_1(173, fn, pfx##173, sfx),	\

	PORT_1(174, fn, pfx##174, sfx),	PORT_1(175, fn, pfx##175, sfx),	\

	PORT_1(176, fn, pfx##176, sfx),	PORT_1(177, fn, pfx##177, sfx),	\

	PORT_1(178, fn, pfx##178, sfx),					\

	/* Port192 - Port222 */						\

	PORT_1(fn, pfx##192, sfx),	PORT_1(fn, pfx##193, sfx),	\

	PORT_1(fn, pfx##194, sfx),	PORT_1(fn, pfx##195, sfx),	\

	PORT_1(fn, pfx##196, sfx),	PORT_1(fn, pfx##197, sfx),	\

	PORT_1(fn, pfx##198, sfx),	PORT_1(fn, pfx##199, sfx),	\

	PORT_10(fn, pfx##20, sfx),					\

	PORT_10(fn, pfx##21, sfx),					\

	PORT_1(fn, pfx##220, sfx),	PORT_1(fn, pfx##221, sfx),	\

	PORT_1(fn, pfx##222, sfx),					\

	PORT_1(192, fn, pfx##192, sfx),	PORT_1(193, fn, pfx##193, sfx),	\

	PORT_1(194, fn, pfx##194, sfx),	PORT_1(195, fn, pfx##195, sfx),	\

	PORT_1(196, fn, pfx##196, sfx),	PORT_1(197, fn, pfx##197, sfx),	\

	PORT_1(198, fn, pfx##198, sfx),	PORT_1(199, fn, pfx##199, sfx),	\

	PORT_10(200, fn, pfx##20, sfx),					\

	PORT_10(210, fn, pfx##21, sfx),					\

	PORT_1(220, fn, pfx##220, sfx),	PORT_1(221, fn, pfx##221, sfx),	\

	PORT_1(222, fn, pfx##222, sfx),					\

	/* Port224 - Port250 */						\

	PORT_1(fn, pfx##224, sfx),	PORT_1(fn, pfx##225, sfx),	\

	PORT_1(fn, pfx##226, sfx),	PORT_1(fn, pfx##227, sfx),	\

	PORT_1(fn, pfx##228, sfx),	PORT_1(fn, pfx##229, sfx),	\

	PORT_10(fn, pfx##23, sfx),					\

	PORT_10(fn, pfx##24, sfx),					\

	PORT_1(fn, pfx##250, sfx),					\

	PORT_1(224, fn, pfx##224, sfx),	PORT_1(225, fn, pfx##225, sfx),	\

	PORT_1(226, fn, pfx##226, sfx),	PORT_1(227, fn, pfx##227, sfx),	\

	PORT_1(228, fn, pfx##228, sfx),	PORT_1(229, fn, pfx##229, sfx),	\

	PORT_10(230, fn, pfx##23, sfx),					\

	PORT_10(240, fn, pfx##24, sfx),					\

	PORT_1(250, fn, pfx##250, sfx),					\

	/* Port256 - Port283 */						\

	PORT_1(fn, pfx##256, sfx),	PORT_1(fn, pfx##257, sfx),	\

	PORT_1(fn, pfx##258, sfx),	PORT_1(fn, pfx##259, sfx),	\

	PORT_10(fn, pfx##26, sfx),					\

	PORT_10(fn, pfx##27, sfx),					\

	PORT_1(fn, pfx##280, sfx),	PORT_1(fn, pfx##281, sfx),	\

	PORT_1(fn, pfx##282, sfx),	PORT_1(fn, pfx##283, sfx),	\

	PORT_1(256, fn, pfx##256, sfx),	PORT_1(257, fn, pfx##257, sfx),	\

	PORT_1(258, fn, pfx##258, sfx),	PORT_1(259, fn, pfx##259, sfx),	\

	PORT_10(260, fn, pfx##26, sfx),					\

	PORT_10(270, fn, pfx##27, sfx),					\

	PORT_1(280, fn, pfx##280, sfx),	PORT_1(281, fn, pfx##281, sfx),	\

	PORT_1(282, fn, pfx##282, sfx),	PORT_1(283, fn, pfx##283, sfx),	\

	/* Port288 - Port308 */						\

	PORT_1(fn, pfx##288, sfx),	PORT_1(fn, pfx##289, sfx),	\

	PORT_10(fn, pfx##29, sfx),					\

	PORT_1(fn, pfx##300, sfx),	PORT_1(fn, pfx##301, sfx),	\

	PORT_1(fn, pfx##302, sfx),	PORT_1(fn, pfx##303, sfx),	\

	PORT_1(fn, pfx##304, sfx),	PORT_1(fn, pfx##305, sfx),	\

	PORT_1(fn, pfx##306, sfx),	PORT_1(fn, pfx##307, sfx),	\

	PORT_1(fn, pfx##308, sfx),					\

	PORT_1(288, fn, pfx##288, sfx),	PORT_1(289, fn, pfx##289, sfx),	\

	PORT_10(290, fn, pfx##29, sfx),					\

	PORT_1(300, fn, pfx##300, sfx),	PORT_1(301, fn, pfx##301, sfx),	\

	PORT_1(302, fn, pfx##302, sfx),	PORT_1(303, fn, pfx##303, sfx),	\

	PORT_1(304, fn, pfx##304, sfx),	PORT_1(305, fn, pfx##305, sfx),	\

	PORT_1(306, fn, pfx##306, sfx),	PORT_1(307, fn, pfx##307, sfx),	\

	PORT_1(308, fn, pfx##308, sfx),					\

	/* Port320 - Port329 */						\

	PORT_10(fn, pfx##32, sfx)

	PORT_10(320, fn, pfx##32, sfx)





enum {
@@ -428,10 +428,7 @@ enum { 
	PINMUX_MARK_END,

};



#define _PORT_DATA(pfx, sfx)	PORT_DATA_IO(pfx)

#define PINMUX_DATA_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)



static const pinmux_enum_t pinmux_data[] = {

static const u16 pinmux_data[] = {

	/* specify valid pin states for each pin in GPIO mode */

	PINMUX_DATA_ALL(),
@@ -1269,19 +1266,12 @@ static const pinmux_enum_t pinmux_data[] = { 
	PINMUX_DATA(IRQ57_MARK,			PORT329_FN0),

};



#define R8A73A4_PIN(pin, cfgs)			\

	{					\

		.name = __stringify(PORT##pin),	\

		.enum_id = PORT##pin##_DATA,	\

		.configs = cfgs,		\

	}



#define __O	(SH_PFC_PIN_CFG_OUTPUT)

#define __IO	(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)

#define __PUD	(SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)



#define R8A73A4_PIN_IO_PU_PD(pin)       R8A73A4_PIN(pin, __IO | __PUD)

#define R8A73A4_PIN_O(pin)              R8A73A4_PIN(pin, __O)

#define R8A73A4_PIN_IO_PU_PD(pin)       SH_PFC_PIN_CFG(pin, __IO | __PUD)

#define R8A73A4_PIN_O(pin)              SH_PFC_PIN_CFG(pin, __O)



static struct sh_pfc_pin pinmux_pins[] = {

	R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
@@ -1408,20 +1398,6 @@ static struct sh_pfc_pin pinmux_pins[] = { 
	R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),

};



static const struct pinmux_range pinmux_ranges[] = {

	{.begin = 0, .end = 30,},

	{.begin = 32, .end = 40,},

	{.begin = 64, .end = 85,},

	{.begin = 96, .end = 126,},

	{.begin = 128, .end = 134,},

	{.begin = 160, .end = 178,},

	{.begin = 192, .end = 222,},

	{.begin = 224, .end = 250,},

	{.begin = 256, .end = 283,},

	{.begin = 288, .end = 308,},

	{.begin = 320, .end = 329,},

};



/* - IRQC ------------------------------------------------------------------- */

#define IRQC_PINS_MUX(pin, irq_mark)				\

static const unsigned int irqc_irq##irq_mark##_pins[] = {	\
@@ -2766,9 +2742,6 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = { 
	.pins = pinmux_pins,

	.nr_pins = ARRAY_SIZE(pinmux_pins),



	.ranges = pinmux_ranges,

	.nr_ranges = ARRAY_SIZE(pinmux_ranges),



	.groups = pinmux_groups,

	.nr_groups = ARRAY_SIZE(pinmux_groups),

	.functions = pinmux_functions,

drivers/pinctrl/sh-pfc/pfc-r8a7740.c

+15 −32
Original line number Diff line number Diff line
@@ -29,17 +29,10 @@ 
#include "sh_pfc.h"



#define CPU_ALL_PORT(fn, pfx, sfx)					\

	PORT_10(fn, pfx, sfx),		PORT_90(fn, pfx, sfx),		\

	PORT_10(fn, pfx##10, sfx),	PORT_90(fn, pfx##1, sfx),	\

	PORT_10(fn, pfx##20, sfx),					\

	PORT_1(fn, pfx##210, sfx),	PORT_1(fn, pfx##211, sfx)



#undef _GPIO_PORT

#define _GPIO_PORT(gpio, sfx)						\

	[gpio] = {							\

		.name = __stringify(PORT##gpio),			\

		.enum_id = PORT##gpio##_DATA,				\

	}

	PORT_10(0,  fn, pfx, sfx),	PORT_90(0,   fn, pfx, sfx),	\

	PORT_10(100, fn, pfx##10, sfx),	PORT_90(100, fn, pfx##1, sfx),	\

	PORT_10(200, fn, pfx##20, sfx),					\

	PORT_1(210, fn, pfx##210, sfx),	PORT_1(211, fn, pfx##211, sfx)



#define IRQC_PIN_MUX(irq, pin)						\

static const unsigned int intc_irq##irq##_pins[] = {			\
@@ -590,11 +583,8 @@ enum { 
	PINMUX_MARK_END,

};



#define _PORT_DATA(pfx, sfx)	PORT_DATA_IO(pfx)

#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_PORT_DATA, , unused)



static const pinmux_enum_t pinmux_data[] = {

	PINMUX_DATA_GP_ALL(),

static const u16 pinmux_data[] = {

	PINMUX_DATA_ALL(),



	/* Port0 */

	PINMUX_DATA(DBGMDT2_MARK,		PORT0_FN1),
@@ -1537,13 +1527,6 @@ static const pinmux_enum_t pinmux_data[] = { 
	PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,			MSEL5CR_30_1,	MSEL5CR_29_0),

};



#define R8A7740_PIN(pin, cfgs)						\

	{								\

		.name = __stringify(PORT##pin),				\

		.enum_id = PORT##pin##_DATA,				\

		.configs = cfgs,					\

	}



#define __I		(SH_PFC_PIN_CFG_INPUT)

#define __O		(SH_PFC_PIN_CFG_OUTPUT)

#define __IO		(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
@@ -1551,15 +1534,15 @@ static const pinmux_enum_t pinmux_data[] = { 
#define __PU		(SH_PFC_PIN_CFG_PULL_UP)

#define __PUD		(SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)



#define R8A7740_PIN_I_PD(pin)		R8A7740_PIN(pin, __I | __PD)

#define R8A7740_PIN_I_PU(pin)		R8A7740_PIN(pin, __I | __PU)

#define R8A7740_PIN_I_PU_PD(pin)		R8A7740_PIN(pin, __I | __PUD)

#define R8A7740_PIN_IO(pin)		R8A7740_PIN(pin, __IO)

#define R8A7740_PIN_IO_PD(pin)		R8A7740_PIN(pin, __IO | __PD)

#define R8A7740_PIN_IO_PU(pin)		R8A7740_PIN(pin, __IO | __PU)

#define R8A7740_PIN_IO_PU_PD(pin)	R8A7740_PIN(pin, __IO | __PUD)

#define R8A7740_PIN_O(pin)		R8A7740_PIN(pin, __O)

#define R8A7740_PIN_O_PU_PD(pin)		R8A7740_PIN(pin, __O | __PUD)

#define R8A7740_PIN_I_PD(pin)		SH_PFC_PIN_CFG(pin, __I | __PD)

#define R8A7740_PIN_I_PU(pin)		SH_PFC_PIN_CFG(pin, __I | __PU)

#define R8A7740_PIN_I_PU_PD(pin)	SH_PFC_PIN_CFG(pin, __I | __PUD)

#define R8A7740_PIN_IO(pin)		SH_PFC_PIN_CFG(pin, __IO)

#define R8A7740_PIN_IO_PD(pin)		SH_PFC_PIN_CFG(pin, __IO | __PD)

#define R8A7740_PIN_IO_PU(pin)		SH_PFC_PIN_CFG(pin, __IO | __PU)

#define R8A7740_PIN_IO_PU_PD(pin)	SH_PFC_PIN_CFG(pin, __IO | __PUD)

#define R8A7740_PIN_O(pin)		SH_PFC_PIN_CFG(pin, __O)

#define R8A7740_PIN_O_PU_PD(pin)	SH_PFC_PIN_CFG(pin, __O | __PUD)



static struct sh_pfc_pin pinmux_pins[] = {

	/* Table 56-1 (I/O and Pull U/D) */