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Commit d975f121 authored by Russell King's avatar Russell King Committed by Chris Ball
Browse files

mmc: sdhci: cache timing information locally 



Rather than reading back the timing information from the registers,
cache it locally.  This allows implementations to translate the UHS
timing by overriding the set_uhs_signaling() method as required
without also having to emulate the SDHCI_HOST_CONTROL2 register.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Tested-by: default avatarMarkus Pargmann <mpa@pengutronix.de>
Tested-by: default avatarStephen Warren <swarren@nvidia.com>
[Ulf Hansson] Resolved conflict
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarChris Ball <chris@printf.net>
parent 96d7b78c

drivers/mmc/host/sdhci.c

+12 −11
Original line number Diff line number Diff line
@@ -1083,24 +1083,23 @@ static void sdhci_finish_command(struct sdhci_host *host) 


static u16 sdhci_get_preset_value(struct sdhci_host *host)

{

	u16 ctrl, preset = 0;

	u16 preset = 0;



	ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);



	switch (ctrl & SDHCI_CTRL_UHS_MASK) {

	case SDHCI_CTRL_UHS_SDR12:

	switch (host->timing) {

	case MMC_TIMING_UHS_SDR12:

		preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);

		break;

	case SDHCI_CTRL_UHS_SDR25:

	case MMC_TIMING_UHS_SDR25:

		preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);

		break;

	case SDHCI_CTRL_UHS_SDR50:

	case MMC_TIMING_UHS_SDR50:

		preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);

		break;

	case SDHCI_CTRL_UHS_SDR104:

	case MMC_TIMING_UHS_SDR104:

	case MMC_TIMING_MMC_HS200:

		preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);

		break;

	case SDHCI_CTRL_UHS_DDR50:

	case MMC_TIMING_UHS_DDR50:

		preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);

		break;

	default:
@@ -1538,6 +1537,7 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) 
		sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);



		host->ops->set_uhs_signaling(host, ios->timing);

		host->timing = ios->timing;



		if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&

				((ios->timing == MMC_TIMING_UHS_SDR12) ||
@@ -1842,12 +1842,13 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) 
	 * If the Host Controller supports the HS200 mode then the

	 * tuning function has to be executed.

	 */

	if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&

	if (host->timing == MMC_TIMING_UHS_SDR50 &&

	    (host->flags & SDHCI_SDR50_NEEDS_TUNING ||

	     host->flags & SDHCI_SDR104_NEEDS_TUNING))

		requires_tuning_nonuhs = true;



	if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||

	if (host->timing == MMC_TIMING_MMC_HS200 ||

	    host->timing == MMC_TIMING_UHS_SDR104 ||

	    requires_tuning_nonuhs)

		ctrl |= SDHCI_CTRL_EXEC_TUNING;

	else {

include/linux/mmc/sdhci.h

+2 −0
Original line number Diff line number Diff line
@@ -172,6 +172,8 @@ struct sdhci_host { 
	unsigned int            ocr_avail_mmc;

	u32 ocr_mask;		/* available voltages */



	unsigned		timing;		/* Current timing */



	u32			thread_isr;



	/* cached registers */