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Commit d93cc222 authored by Borislav Petkov's avatar Borislav Petkov
Browse files

EDAC, AMD: carve out decoding of MCi_STATUS ErrorCode 



This is the MCE error code from the MCi_STATUS banks, bits [15:0] which
describe what type of error was encountered: GART TLB, Memory or Bus
error. The semantics of those bits are identical across all MCE banks so
decode those separately, irrespectively of MCE type.

Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
parent b69b29de

drivers/edac/amd64_edac.c

+0 −4
Original line number Diff line number Diff line
@@ -2289,10 +2289,6 @@ static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci, 
	u32 xec = EXT_ERROR_CODE(info->nbsl);

	int ecc_type = info->nbsh & (0x3 << 13);



	pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, %s\n",

		 RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec), PP_MSG(ec));





	/* Bail early out if this was an 'observed' error */

	if (PP(ec) == K8_NBSL_PP_OBS)

		return;

drivers/edac/edac_mce_amd.c

+22 −15
Original line number Diff line number Diff line
@@ -150,6 +150,16 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) 
		pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf)));

	}





	pr_emerg("%s.\n", EXT_ERR_MSG(xec));



	if (BUS_ERROR(ec) && nb_bus_decoder)

		nb_bus_decoder(node_id, regs);

}

EXPORT_SYMBOL_GPL(amd_decode_nb_mce);



static inline void amd_decode_err_code(unsigned int ec)

{

	if (TLB_ERROR(ec)) {

		/*

		 * GART errors are intended to help graphics driver developers
@@ -166,33 +176,28 @@ void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors) 
		if (!report_gart_errors)

			return;



		pr_emerg(" GART TLB error, Transaction: %s, Cache Level %s\n",

		pr_emerg(" Transaction: %s, Cache Level %s\n",

			 TT_MSG(ec), LL_MSG(ec));

	} else if (MEM_ERROR(ec)) {

		pr_emerg(" Memory/Cache error, Transaction: %s, Type: %s,"

			 " Cache Level: %s",

		pr_emerg(" Transaction: %s, Type: %s, Cache Level: %s",

			 RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));

	} else if (BUS_ERROR(ec)) {

		pr_emerg(" Bus (Link/DRAM) error\n");

		if (nb_bus_decoder)

			nb_bus_decoder(node_id, regs);

	} else {

		/* shouldn't reach here! */

		pr_warning("%s: unknown MCE error 0x%x\n", __func__, ec);

		pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, "

			 "Participating Processor: %s\n",

			  RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),

			  PP_MSG(ec));

	} else

		pr_warning("Huh? Unknown MCE error 0x%x\n", ec);

}



	pr_emerg("%s.\n", EXT_ERR_MSG(xec));

}

EXPORT_SYMBOL_GPL(amd_decode_nb_mce);



void decode_mce(struct mce *m)

{

	struct err_regs regs;

	int node, ecc;



	pr_emerg("MC%d_STATUS:\n", m->bank);

	pr_emerg("MC%d_STATUS: ", m->bank);



	pr_emerg(" Error: %sorrected, Report: %s, MiscV: %svalid, "

	pr_cont("%sorrected error, report: %s, MiscV: %svalid, "

		 "CPU context corrupt: %s",

		 ((m->status & MCI_STATUS_UC) ? "Unc"  : "C"),

		 ((m->status & MCI_STATUS_EN) ? "yes"  : "no"),
@@ -206,6 +211,8 @@ void decode_mce(struct mce *m) 


	pr_cont("\n");



	amd_decode_err_code(m->status & 0xffff);



	if (m->bank == 4) {

		regs.nbsl  = (u32) m->status;

		regs.nbsh  = (u32)(m->status >> 32);