Merge branch 'clk-shmobile-for-v4.5' of... (d90e1496) · Commits · e / devices / android_kernel_teracube_2e

Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt

+4 −0

Original line number	Original line	Diff line number	Diff line
	@@ -20,6 +20,10 @@ Required Properties:
	clocks must be specified. For clocks with multiple parents, invalid		clocks must be specified. For clocks with multiple parents, invalid
	settings must be specified as "<0>".		settings must be specified as "<0>".
	- #clock-cells: Must be 0		- #clock-cells: Must be 0


			Optional Properties:

	- clock-output-names: The name of the clock as a free-form string		- clock-output-names: The name of the clock as a free-form string

drivers/clk/Makefile

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -71,6 +71,7 @@ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
	obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/		obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
	obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/		obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
	obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/		obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/
			obj-$(CONFIG_ARCH_RENESAS) += shmobile/
	obj-$(CONFIG_ARCH_SIRF) += sirf/		obj-$(CONFIG_ARCH_SIRF) += sirf/
	obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/		obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
	obj-$(CONFIG_PLAT_SPEAR) += spear/		obj-$(CONFIG_PLAT_SPEAR) += spear/

drivers/clk/shmobile/Makefile

+12 −12

Original line number	Original line	Diff line number	Diff line
	obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o		obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
	obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o		obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o clk-mstp.o
	obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o		obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-mstp.o clk-div6.o
	obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o		obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-mstp.o clk-div6.o
	obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o		obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o clk-mstp.o
	obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o		obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o clk-mstp.o
	obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o		obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
	obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o		obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
	obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o		obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
	obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o		obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
	obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o		obj-$(CONFIG_ARCH_R8A7795) += renesas-cpg-mssr.o \
	obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o		r8a7795-cpg-mssr.o clk-div6.o
	obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-mstp.o		obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-mstp.o clk-div6.o

drivers/clk/shmobile/clk-div6.c

+86 −51

Original line number	Original line	Diff line number	Diff line
	@@ -18,6 +18,8 @@
	#include <linux/of_address.h>		#include <linux/of_address.h>
	#include <linux/slab.h>		#include <linux/slab.h>

			#include "clk-div6.h"

	#define CPG_DIV6_CKSTP BIT(8)		#define CPG_DIV6_CKSTP BIT(8)
	#define CPG_DIV6_DIV(d) ((d) & 0x3f)		#define CPG_DIV6_DIV(d) ((d) & 0x3f)
	#define CPG_DIV6_DIV_MASK 0x3f		#define CPG_DIV6_DIV_MASK 0x3f
	@@ -172,66 +174,43 @@ static const struct clk_ops cpg_div6_clock_ops = {
	.set_rate = cpg_div6_clock_set_rate,		.set_rate = cpg_div6_clock_set_rate,
	};		};

	static void __init cpg_div6_clock_init(struct device_node *np)
			/**
			* cpg_div6_register - Register a DIV6 clock
			* @name: Name of the DIV6 clock
			* @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
			* @parent_names: Array containing the names of the parent clocks
			* @reg: Mapped register used to control the DIV6 clock
			*/
			struct clk * __init cpg_div6_register(const char *name,
			unsigned int num_parents,
			const char **parent_names,
			void __iomem *reg)
	{		{
	unsigned int num_parents, valid_parents;		unsigned int valid_parents;
	const char **parent_names;
	struct clk_init_data init;		struct clk_init_data init;
	struct div6_clock *clock;		struct div6_clock *clock;
	const char *name;
	struct clk *clk;		struct clk *clk;
	unsigned int i;		unsigned int i;
	int ret;

	clock = kzalloc(sizeof(*clock), GFP_KERNEL);		clock = kzalloc(sizeof(*clock), GFP_KERNEL);
	if (!clock)		if (!clock)
	return;		return ERR_PTR(-ENOMEM);

	num_parents = of_clk_get_parent_count(np);
	if (num_parents < 1) {
	pr_err("%s: no parent found for %s DIV6 clock\n",
	__func__, np->name);
	return;
	}

	clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),		clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
	GFP_KERNEL);		GFP_KERNEL);
	parent_names = kmalloc_array(num_parents, sizeof(*parent_names),		if (!clock->parents) {
	GFP_KERNEL);		clk = ERR_PTR(-ENOMEM);
	if (!parent_names)		goto free_clock;
	return;

	/* Remap the clock register and read the divisor. Disabling the
	* clock overwrites the divisor, so we need to cache its value for the
	* enable operation.
	*/
	clock->reg = of_iomap(np, 0);
	if (clock->reg == NULL) {
	pr_err("%s: failed to map %s DIV6 clock register\n",
	__func__, np->name);
	goto error;
	}

	clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;

	/* Parse the DT properties. */
	ret = of_property_read_string(np, "clock-output-names", &name);
	if (ret < 0) {
	pr_err("%s: failed to get %s DIV6 clock output name\n",
	__func__, np->name);
	goto error;
	}		}

			clock->reg = reg;

	for (i = 0, valid_parents = 0; i < num_parents; i++) {		/*
	const char *name = of_clk_get_parent_name(np, i);		* Read the divisor. Disabling the clock overwrites the divisor, so we
			* need to cache its value for the enable operation.
	if (name) {		*/
	parent_names[valid_parents] = name;		clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
	clock->parents[valid_parents] = i;
	valid_parents++;
	}
	}

	switch (num_parents) {		switch (num_parents) {
	case 1:		case 1:
	@@ -250,8 +229,18 @@ static void __init cpg_div6_clock_init(struct device_node *np)
	break;		break;
	default:		default:
	pr_err("%s: invalid number of parents for DIV6 clock %s\n",		pr_err("%s: invalid number of parents for DIV6 clock %s\n",
	__func__, np->name);		__func__, name);
	goto error;		clk = ERR_PTR(-EINVAL);
			goto free_parents;
			}

			/* Filter out invalid parents */
			for (i = 0, valid_parents = 0; i < num_parents; i++) {
			if (parent_names[i]) {
			parent_names[valid_parents] = parent_names[i];
			clock->parents[valid_parents] = i;
			valid_parents++;
			}
	}		}

	/* Register the clock. */		/* Register the clock. */
	@@ -264,6 +253,53 @@ static void __init cpg_div6_clock_init(struct device_node *np)
	clock->hw.init = &init;		clock->hw.init = &init;

	clk = clk_register(NULL, &clock->hw);		clk = clk_register(NULL, &clock->hw);
			if (IS_ERR(clk))
			goto free_parents;

			return clk;

			free_parents:
			kfree(clock->parents);
			free_clock:
			kfree(clock);
			return clk;
			}

			static void __init cpg_div6_clock_init(struct device_node *np)
			{
			unsigned int num_parents;
			const char **parent_names;
			const char *clk_name = np->name;
			void __iomem *reg;
			struct clk *clk;
			unsigned int i;

			num_parents = of_clk_get_parent_count(np);
			if (num_parents < 1) {
			pr_err("%s: no parent found for %s DIV6 clock\n",
			__func__, np->name);
			return;
			}

			parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
			GFP_KERNEL);
			if (!parent_names)
			return;

			reg = of_iomap(np, 0);
			if (reg == NULL) {
			pr_err("%s: failed to map %s DIV6 clock register\n",
			__func__, np->name);
			goto error;
			}

			/* Parse the DT properties. */
			of_property_read_string(np, "clock-output-names", &clk_name);

			for (i = 0; i < num_parents; i++)
			parent_names[i] = of_clk_get_parent_name(np, i);

			clk = cpg_div6_register(clk_name, num_parents, parent_names, reg);
	if (IS_ERR(clk)) {		if (IS_ERR(clk)) {
	pr_err("%s: failed to register %s DIV6 clock (%ld)\n",		pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
	__func__, np->name, PTR_ERR(clk));		__func__, np->name, PTR_ERR(clk));
	@@ -276,9 +312,8 @@ static void __init cpg_div6_clock_init(struct device_node *np)
	return;		return;

	error:		error:
	if (clock->reg)		if (reg)
	iounmap(clock->reg);		iounmap(reg);
	kfree(parent_names);		kfree(parent_names);
	kfree(clock);
	}		}
	CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);		CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);

drivers/clk/shmobile/clk-div6.h

0 → 100644

+7 −0

Original line number	Original line	Diff line number	Diff line
			#ifndef __SHMOBILE_CLK_DIV6_H__
			#define __SHMOBILE_CLK_DIV6_H__

			struct clk cpg_div6_register(const char name, unsigned int num_parents,
			const char *parent_names, void __iomem reg);

			#endif