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Commit d90125bf authored by Linus Torvalds's avatar Linus Torvalds
Browse files
* 'i915fb' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/intelfb-2.6: (25 commits)
  intelfb: fixup clock calculation debugging.
  Removed hard coded EDID buffer size.
  intelfb: use regular modedb table instead of VESA
  intelfb: use firmware EDID for mode database
  Revert "intelfb driver -- use the regular modedb table instead of the VESA"
  intelfb: int option fix
  sync modesetting code with X.org
  intelfb: align with changes from my X driver.
  intelfb driver -- use the regular modedb table instead of the VESA
  Adds support for 256MB aperture on 945 chipsets to the intelfb driver
  intelfb -- uses stride alignment of 64 on the 9xx chipsets.
  intelfb: some cleanups for intelfbhw
  intelfb: fixup pitch calculation like X does
  intelfb: fixup p calculation
  This patch makes a needlessly global struct static.
  intelfb: add i945GM support
  intelfb: fixup whitespace..
  intelfb: add hw cursor support for i9xx
  intelfb: make i915 modeset
  intelfb: add support for i945G
  ...
parents bfd189a8 2abac1db
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+1 −1
Original line number Diff line number Diff line
@@ -743,7 +743,7 @@ config FB_I810_I2C

config FB_INTEL
	tristate "Intel 830M/845G/852GM/855GM/865G support (EXPERIMENTAL)"
	depends on FB && EXPERIMENTAL && PCI && X86_32
	depends on FB && EXPERIMENTAL && PCI && X86
	select AGP
	select AGP_INTEL
	select FB_MODE_HELPERS
+13 −3
Original line number Diff line number Diff line
@@ -8,9 +8,9 @@


/*** Version/name ***/
#define INTELFB_VERSION			"0.9.2"
#define INTELFB_VERSION			"0.9.4"
#define INTELFB_MODULE_NAME		"intelfb"
#define SUPPORTED_CHIPSETS		"830M/845G/852GM/855GM/865G/915G/915GM"
#define SUPPORTED_CHIPSETS		"830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM"


/*** Debug/feature defines ***/
@@ -52,11 +52,14 @@
#define PCI_DEVICE_ID_INTEL_865G	0x2572
#define PCI_DEVICE_ID_INTEL_915G	0x2582
#define PCI_DEVICE_ID_INTEL_915GM	0x2592
#define PCI_DEVICE_ID_INTEL_945G	0x2772
#define PCI_DEVICE_ID_INTEL_945GM	0x27A2

/* Size of MMIO region */
#define INTEL_REG_SIZE			0x80000

#define STRIDE_ALIGNMENT		16
#define STRIDE_ALIGNMENT_I9XX		64

#define PALETTE_8_ENTRIES		256

@@ -125,7 +128,9 @@ enum intel_chips {
	INTEL_855GME,
	INTEL_865G,
	INTEL_915G,
	INTEL_915GM
	INTEL_915GM,
	INTEL_945G,
	INTEL_945GM,
};

struct intelfb_hwstate {
@@ -277,8 +282,13 @@ struct intelfb_info {

	/* driver registered */
	int registered;
	
	/* index into plls */
	int pll_index;
};

#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G)||(dinfo->chipset == INTEL_915GM)||((dinfo)->chipset == INTEL_945G)||(dinfo->chipset==INTEL_945GM))

/*** function prototypes ***/

extern int intelfb_var_to_depth(const struct fb_var_screeninfo *var);
+69 −16
Original line number Diff line number Diff line
/*
 * intelfb
 *
 * Linux framebuffer driver for Intel(R) 830M/845G/852GM/855GM/865G/915G/915GM
 * integrated graphics chips.
 * Linux framebuffer driver for Intel(R) 830M/845G/852GM/855GM/865G/915G/915GM/
 * 945G/945GM integrated graphics chips.
 *
 * Copyright  2002, 2003 David Dawes <dawes@xfree86.org>
 *                   2004 Sylvain Meyer
 *                   2006 David Airlie
 *
 * This driver consists of two parts.  The first part (intelfbdrv.c) provides
 * the basic fbdev interfaces, is derived in part from the radeonfb and
@@ -131,6 +132,7 @@

#include "intelfb.h"
#include "intelfbhw.h"
#include "../edid.h"

static void __devinit get_initial_mode(struct intelfb_info *dinfo);
static void update_dinfo(struct intelfb_info *dinfo,
@@ -182,6 +184,8 @@ static struct pci_device_id intelfb_pci_table[] __devinitdata = {
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_865G, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_865G },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_915G, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_915G },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_915GM, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_915GM },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_945G, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_945G },
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_945GM, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, INTELFB_CLASS_MASK, INTEL_945GM },
	{ 0, }
};

@@ -261,7 +265,7 @@ MODULE_PARM_DESC(mode,

#ifndef MODULE
#define OPT_EQUAL(opt, name) (!strncmp(opt, name, strlen(name)))
#define OPT_INTVAL(opt, name) simple_strtoul(opt + strlen(name), NULL, 0)
#define OPT_INTVAL(opt, name) simple_strtoul(opt + strlen(name) + 1, NULL, 0)
#define OPT_STRVAL(opt, name) (opt + strlen(name))

static __inline__ char *
@@ -546,11 +550,11 @@ intelfb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)

	/* Set base addresses. */
	if ((ent->device == PCI_DEVICE_ID_INTEL_915G) ||
			(ent->device == PCI_DEVICE_ID_INTEL_915GM)) {
	    (ent->device == PCI_DEVICE_ID_INTEL_915GM) ||
	    (ent->device == PCI_DEVICE_ID_INTEL_945G)  ||
	    (ent->device == PCI_DEVICE_ID_INTEL_945GM)) {
		aperture_bar = 2;
		mmio_bar = 0;
		/* Disable HW cursor on 915G/M (not implemented yet) */
		hwcursor = 0;
	}
	dinfo->aperture.physical = pci_resource_start(pdev, aperture_bar);
	dinfo->aperture.size     = pci_resource_len(pdev, aperture_bar);
@@ -584,8 +588,7 @@ intelfb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
	/* Get the chipset info. */
	dinfo->pci_chipset = pdev->device;

	if (intelfbhw_get_chipset(pdev, &dinfo->name, &dinfo->chipset,
				  &dinfo->mobile)) {
	if (intelfbhw_get_chipset(pdev, dinfo)) {
		cleanup(dinfo);
		return -ENODEV;
	}
@@ -1029,17 +1032,44 @@ intelfb_init_var(struct intelfb_info *dinfo)
		       sizeof(struct fb_var_screeninfo));
		msrc = 5;
	} else {
		const u8 *edid_s = fb_firmware_edid(&dinfo->pdev->dev);
		u8 *edid_d = NULL;

		if (edid_s) {
			edid_d = kmalloc(EDID_LENGTH, GFP_KERNEL);

			if (edid_d) {
				memcpy(edid_d, edid_s, EDID_LENGTH);
				fb_edid_to_monspecs(edid_d,
						    &dinfo->info->monspecs);
				kfree(edid_d);
			}
		}

		if (mode) {
			printk("intelfb: Looking for mode in private "
			       "database\n");
			msrc = fb_find_mode(var, dinfo->info, mode,
					    vesa_modes, VESA_MODEDB_SIZE,
					    dinfo->info->monspecs.modedb,
					    dinfo->info->monspecs.modedb_len,
					    NULL, 0);

			if (msrc && msrc > 1) {
				printk("intelfb: No mode in private database, "
				       "intelfb: looking for mode in global "
				       "database ");
				msrc = fb_find_mode(var, dinfo->info, mode,
						    NULL, 0, NULL, 0);

				if (msrc)
					msrc |= 8;
			}

		}

		if (!msrc) {
			msrc = fb_find_mode(var, dinfo->info, PREFERRED_MODE,
					    vesa_modes, VESA_MODEDB_SIZE,
					    NULL, 0);
					    NULL, 0, NULL, 0);
		}
	}

@@ -1139,6 +1169,9 @@ update_dinfo(struct intelfb_info *dinfo, struct fb_var_screeninfo *var)
	}

	/* Make sure the line length is a aligned correctly. */
	if (IS_I9XX(dinfo))
		dinfo->pitch = ROUND_UP_TO(dinfo->pitch, STRIDE_ALIGNMENT_I9XX);
	else
		dinfo->pitch = ROUND_UP_TO(dinfo->pitch, STRIDE_ALIGNMENT);

	if (FIXED_MODE(dinfo))
@@ -1162,16 +1195,33 @@ intelfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
	struct fb_var_screeninfo v;
	struct intelfb_info *dinfo;
	static int first = 1;
	int i;
	/* Good pitches to allow tiling.  Don't care about pitches < 1024. */
	static const int pitches[] = {
		128 * 8,
		128 * 16,
		128 * 32,
		128 * 64,
		0
	};

	DBG_MSG("intelfb_check_var: accel_flags is %d\n", var->accel_flags);

	dinfo = GET_DINFO(info);

	/* update the pitch */
	if (intelfbhw_validate_mode(dinfo, var) != 0)
		return -EINVAL;

	v = *var;

	for (i = 0; pitches[i] != 0; i++) {
		if (pitches[i] >= v.xres_virtual) {
			v.xres_virtual = pitches[i];
			break;
		}
	}

	/* Check for a supported bpp. */
	if (v.bits_per_pixel <= 8) {
		v.bits_per_pixel = 8;
@@ -1467,7 +1517,7 @@ static int
intelfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
        struct intelfb_info *dinfo = GET_DINFO(info);

	u32 physical;
#if VERBOSE > 0
	DBG_MSG("intelfb_cursor\n");
#endif
@@ -1478,7 +1528,10 @@ intelfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
	intelfbhw_cursor_hide(dinfo);

	/* If XFree killed the cursor - restore it */
	if (INREG(CURSOR_A_BASEADDR) != dinfo->cursor.offset << 12) {
	physical = (dinfo->mobile || IS_I9XX(dinfo)) ? dinfo->cursor.physical :
		   (dinfo->cursor.offset << 12);

	if (INREG(CURSOR_A_BASEADDR) != physical) {
		u32 fg, bg;

		DBG_MSG("the cursor was killed - restore it !!\n");
+327 −167

File changed.

Preview size limit exceeded, changes collapsed.

+2 −23
Original line number Diff line number Diff line
@@ -133,6 +133,7 @@
#define DPLL_VGA_MODE_DISABLE		(1 << 28)
#define DPLL_P2_MASK			1
#define DPLL_P2_SHIFT			23
#define DPLL_I9XX_P2_SHIFT              24
#define DPLL_P1_FORCE_DIV2		(1 << 21)
#define DPLL_P1_MASK			0x1f
#define DPLL_P1_SHIFT			16
@@ -155,29 +156,8 @@
/* PLL parameters (these are for 852GM/855GM/865G, check earlier chips). */
/* Clock values are in units of kHz */
#define PLL_REFCLK		48000
#define MIN_VCO_FREQ		930000
#define MAX_VCO_FREQ		1400000
#define MIN_CLOCK		25000
#define MAX_CLOCK		350000
#define P_TRANSITION_CLOCK	165000
#define MIN_M			108
#define MAX_M			140
#define MIN_M1			18
#define MAX_M1			26
#define MIN_M2			6
#define MAX_M2			16
#define MIN_P			4
#define MAX_P			128
#define MIN_P1			0
#define MAX_P1			31
#define MIN_N			3
#define MAX_N			16

#define CALC_VCLOCK(m1, m2, n, p1, p2) \
        ((PLL_REFCLK * (5 * ((m1) + 2) + ((m2) + 2)) / ((n) + 2)) / \
        (((p1) + 2) * (1 << (p2 + 1))))

#define CALC_VCLOCK3(m, n, p)	((PLL_REFCLK * (m) / (n)) / (p))

/* Two pipes */
#define PIPE_A			0
@@ -522,8 +502,7 @@


/* function protoypes */
extern int intelfbhw_get_chipset(struct pci_dev *pdev, const char **name,
				 int *chipset, int *mobile);
extern int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo);
extern int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
				int *stolen_size);
extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo);