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Commit d8f64797 authored by Stephen Warren's avatar Stephen Warren
Browse files

ARM: tegra: add missing clock documentation to DT bindings 



Many of the Tegra DT binding documents say nothing about the clocks or
clock-names properties, yet those are present and required in DT files.
This patch simply updates the documentation file to match the implicit
definition of the binding, based on real-world DT content.

All Tegra bindings that mention clocks are updated to have consistent
wording and formatting of the clock-related properties.

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Acked-By: default avatarTerje Bergstrom <tbergstrom@nvidia.com>
parent e9827d9b

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Required properties: 
- compatible : Should contain "nvidia,tegra<chip>-pmc".

- reg : Offset and length of the register set for the device

- clocks : Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names : Must include the following entries:

  "pclk" (The Tegra clock of that name),

  "clk32k_in" (The 32KHz clock input to Tegra).

Documentation/devicetree/bindings/dma/tegra20-apbdma.txt

+3 −0
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ Required properties: 
- reg: Should contain DMA registers location and length. This shuld include

  all of the per-channel registers.

- interrupts: Should contain all of the per-channel DMA interrupts.

- clocks: Must contain one entry, for the module clock.

  See ../clocks/clock-bindings.txt for details.



Examples:
@@ -27,4 +29,5 @@ apbdma: dma@6000a000 { 
		       0 149 0x04

		       0 150 0x04

		       0 151 0x04 >;

	clocks = <&tegra_car 34>;

};

Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt

+59 −0
Original line number Diff line number Diff line
@@ -9,6 +9,8 @@ Required properties: 
- #size-cells: The number of cells used to represent the size of an address

  range in the host1x address space. Should be 1.

- ranges: The mapping of the host1x address space to the CPU address space.

- clocks: Must contain one entry, for the module clock.

  See ../clocks/clock-bindings.txt for details.



The host1x top-level node defines a number of children, each representing one

of the following host1x client modules:
@@ -19,6 +21,8 @@ of the following host1x client modules: 
  - compatible: "nvidia,tegra<chip>-mpe"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.

  - clocks: Must contain one entry, for the module clock.

    See ../clocks/clock-bindings.txt for details.



- vi: video input
@@ -26,6 +30,8 @@ of the following host1x client modules: 
  - compatible: "nvidia,tegra<chip>-vi"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.

  - clocks: Must contain one entry, for the module clock.

    See ../clocks/clock-bindings.txt for details.



- epp: encoder pre-processor
@@ -33,6 +39,8 @@ of the following host1x client modules: 
  - compatible: "nvidia,tegra<chip>-epp"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.

  - clocks: Must contain one entry, for the module clock.

    See ../clocks/clock-bindings.txt for details.



- isp: image signal processor
@@ -40,6 +48,8 @@ of the following host1x client modules: 
  - compatible: "nvidia,tegra<chip>-isp"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.

  - clocks: Must contain one entry, for the module clock.

    See ../clocks/clock-bindings.txt for details.



- gr2d: 2D graphics engine
@@ -47,12 +57,21 @@ of the following host1x client modules: 
  - compatible: "nvidia,tegra<chip>-gr2d"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.

  - clocks: Must contain one entry, for the module clock.

    See ../clocks/clock-bindings.txt for details.



- gr3d: 3D graphics engine



  Required properties:

  - compatible: "nvidia,tegra<chip>-gr3d"

  - reg: Physical base address and length of the controller's registers.

  - clocks: Must contain an entry for each entry in clock-names.

    See ../clocks/clock-bindings.txt for details.

  - clock-names: Must include the following entries:

    (This property may be omitted if the only clock in the list is "3d")

    - 3d

      This MUST be the first entry.

    - 3d2 (Only required on SoCs with two 3D clocks)



- dc: display controller
@@ -60,6 +79,12 @@ of the following host1x client modules: 
  - compatible: "nvidia,tegra<chip>-dc"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.

  - clocks: Must contain an entry for each entry in clock-names.

    See ../clocks/clock-bindings.txt for details.

  - clock-names: Must include the following entries:

    - dc

      This MUST be the first entry.

    - parent



  Each display controller node has a child node, named "rgb", that represents

  the RGB output associated with the controller. It can take the following
@@ -76,6 +101,12 @@ of the following host1x client modules: 
  - interrupts: The interrupt outputs from the controller.

  - vdd-supply: regulator for supply voltage

  - pll-supply: regulator for PLL

  - clocks: Must contain an entry for each entry in clock-names.

    See ../clocks/clock-bindings.txt for details.

  - clock-names: Must include the following entries:

    - hdmi

      This MUST be the first entry.

    - parent



  Optional properties:

  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
@@ -88,12 +119,20 @@ of the following host1x client modules: 
  - compatible: "nvidia,tegra<chip>-tvo"

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.

  - clocks: Must contain one entry, for the module clock.

    See ../clocks/clock-bindings.txt for details.



- dsi: display serial interface



  Required properties:

  - compatible: "nvidia,tegra<chip>-dsi"

  - reg: Physical base address and length of the controller's registers.

  - clocks: Must contain an entry for each entry in clock-names.

    See ../clocks/clock-bindings.txt for details.

  - clock-names: Must include the following entries:

    - dsi

      This MUST be the first entry.

    - parent



Example:
@@ -105,6 +144,7 @@ Example: 
		reg = <0x50000000 0x00024000>;

		interrupts = <0 65 0x04   /* mpcore syncpt */

			      0 67 0x04>; /* mpcore general */

		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;



		#address-cells = <1>;

		#size-cells = <1>;
@@ -115,41 +155,50 @@ Example: 
			compatible = "nvidia,tegra20-mpe";

			reg = <0x54040000 0x00040000>;

			interrupts = <0 68 0x04>;

			clocks = <&tegra_car TEGRA20_CLK_MPE>;

		};



		vi {

			compatible = "nvidia,tegra20-vi";

			reg = <0x54080000 0x00040000>;

			interrupts = <0 69 0x04>;

			clocks = <&tegra_car TEGRA20_CLK_VI>;

		};



		epp {

			compatible = "nvidia,tegra20-epp";

			reg = <0x540c0000 0x00040000>;

			interrupts = <0 70 0x04>;

			clocks = <&tegra_car TEGRA20_CLK_EPP>;

		};



		isp {

			compatible = "nvidia,tegra20-isp";

			reg = <0x54100000 0x00040000>;

			interrupts = <0 71 0x04>;

			clocks = <&tegra_car TEGRA20_CLK_ISP>;

		};



		gr2d {

			compatible = "nvidia,tegra20-gr2d";

			reg = <0x54140000 0x00040000>;

			interrupts = <0 72 0x04>;

			clocks = <&tegra_car TEGRA20_CLK_GR2D>;

		};



		gr3d {

			compatible = "nvidia,tegra20-gr3d";

			reg = <0x54180000 0x00040000>;

			clocks = <&tegra_car TEGRA20_CLK_GR3D>;

		};



		dc@54200000 {

			compatible = "nvidia,tegra20-dc";

			reg = <0x54200000 0x00040000>;

			interrupts = <0 73 0x04>;

			clocks = <&tegra_car TEGRA20_CLK_DISP1>,

				 <&tegra_car TEGRA20_CLK_PLL_P>;

			clock-names = "disp1", "parent";



			rgb {

				status = "disabled";
@@ -160,6 +209,9 @@ Example: 
			compatible = "nvidia,tegra20-dc";

			reg = <0x54240000 0x00040000>;

			interrupts = <0 74 0x04>;

			clocks = <&tegra_car TEGRA20_CLK_DISP2>,

				 <&tegra_car TEGRA20_CLK_PLL_P>;

			clock-names = "disp2", "parent";



			rgb {

				status = "disabled";
@@ -170,6 +222,9 @@ Example: 
			compatible = "nvidia,tegra20-hdmi";

			reg = <0x54280000 0x00040000>;

			interrupts = <0 75 0x04>;

			clocks = <&tegra_car TEGRA20_CLK_HDMI>,

				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;

			clock-names = "hdmi", "parent";

			status = "disabled";

		};
@@ -177,12 +232,16 @@ Example: 
			compatible = "nvidia,tegra20-tvo";

			reg = <0x542c0000 0x00040000>;

			interrupts = <0 76 0x04>;

			clocks = <&tegra_car TEGRA20_CLK_TVO>;

			status = "disabled";

		};



		dsi {

			compatible = "nvidia,tegra20-dsi";

			reg = <0x54300000 0x00040000>;

			clocks = <&tegra_car TEGRA20_CLK_DSI>,

				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;

			clock-names = "dsi", "parent";

			status = "disabled";

		};

	};

Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt

+8 −6
Original line number Diff line number Diff line
@@ -39,12 +39,14 @@ Required properties: 
- interrupts: Should contain I2C controller interrupts.

- address-cells: Address cells for I2C device address.

- size-cells: Size of the I2C device address.

- clocks: Clock ID as per

		Documentation/devicetree/bindings/clock/tegra<chip-id>.txt

	for I2C controller.

- clock-names: Name of the clock:

	Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk".

	Tegra114 I2C controller: "div-clk".

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  Tegra20/Tegra30:

  - div-clk

  - fast-clk

  Tegra114:

  - div-clk



Example:

Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt

+3 −0
Original line number Diff line number Diff line
@@ -13,6 +13,8 @@ Required properties: 
  array of pin numbers which is used as column.

- linux,keymap: The keymap for keys as described in the binding document

  devicetree/bindings/input/matrix-keymap.txt.

- clocks: Must contain one entry, for the module clock.

  See ../clocks/clock-bindings.txt for details.



Optional properties, in addition to those specified by the shared

matrix-keyboard bindings:
@@ -31,6 +33,7 @@ keyboard: keyboard { 
	compatible = "nvidia,tegra20-kbc";

	reg = <0x7000e200 0x100>;

	interrupts = <0 85 0x04>;

	clocks = <&tegra_car 36>;

	nvidia,ghost-filter;

	nvidia,debounce-delay-ms = <640>;

	nvidia,kbc-row-pins = <0 1 2>;    /* pin 0, 1, 2 as rows */