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Commit d8d42b05 authored by Michael Ellerman's avatar Michael Ellerman
Browse files

powerpc/64: Do load of PACAKBASE in LOAD_HANDLER 



The LOAD_HANDLER macro requires that you have previously loaded "reg"
with PACAKBASE. Although that gives callers flexibility to get PACAKBASE
in some interesting way, none of the callers actually do that. So fold
the load of PACAKBASE into the macro, making it simpler for callers to
use correctly.

Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Reviewed-by: default avatarNick Piggin <npiggin@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 27510235

arch/powerpc/include/asm/exception-64s.h

+1 −2
Original line number Original line Diff line number Diff line
@@ -52,7 +52,6 @@ 




#ifdef CONFIG_RELOCATABLE

#ifdef CONFIG_RELOCATABLE

#define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h)			\

#define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h)			\

	ld	r12,PACAKBASE(r13);	/* get high part of &label */	\

	mfspr	r11,SPRN_##h##SRR0;	/* save SRR0 */			\

	mfspr	r11,SPRN_##h##SRR0;	/* save SRR0 */			\

	LOAD_HANDLER(r12,label);					\

	LOAD_HANDLER(r12,label);					\

	mtctr	r12;							\

	mtctr	r12;							\
@@ -90,6 +89,7 @@ 
 * that kernelbase be 64K aligned.

 * that kernelbase be 64K aligned.

 */

 */

#define LOAD_HANDLER(reg, label)					\

#define LOAD_HANDLER(reg, label)					\

	ld	reg,PACAKBASE(r13);	/* get high part of &label */	\

	ori	reg,reg,(label)-_stext;	/* virt addr of handler ... */

	ori	reg,reg,(label)-_stext;	/* virt addr of handler ... */





/* Exception register prefixes */

/* Exception register prefixes */
@@ -175,7 +175,6 @@ END_FTR_SECTION_NESTED(ftr,ftr,943) 
	__EXCEPTION_PROLOG_1(area, extra, vec)

	__EXCEPTION_PROLOG_1(area, extra, vec)





#define __EXCEPTION_PROLOG_PSERIES_1(label, h)				\

#define __EXCEPTION_PROLOG_PSERIES_1(label, h)				\

	ld	r12,PACAKBASE(r13);	/* get high part of &label */	\

	ld	r10,PACAKMSR(r13);	/* get MSR value for kernel */	\

	ld	r10,PACAKMSR(r13);	/* get MSR value for kernel */	\

	mfspr	r11,SPRN_##h##SRR0;	/* save SRR0 */			\

	mfspr	r11,SPRN_##h##SRR0;	/* save SRR0 */			\

	LOAD_HANDLER(r12,label)						\

	LOAD_HANDLER(r12,label)						\

arch/powerpc/kernel/exceptions-64s.S

+0 −12
Original line number Original line Diff line number Diff line
@@ -41,7 +41,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ 




#define SYSCALL_PSERIES_2_RFID 					\

#define SYSCALL_PSERIES_2_RFID 					\

	mfspr	r12,SPRN_SRR1 ;					\

	mfspr	r12,SPRN_SRR1 ;					\

	ld	r10,PACAKBASE(r13) ; 				\

	LOAD_HANDLER(r10, system_call_entry) ; 			\

	LOAD_HANDLER(r10, system_call_entry) ; 			\

	mtspr	SPRN_SRR0,r10 ; 				\

	mtspr	SPRN_SRR0,r10 ; 				\

	ld	r10,PACAKMSR(r13) ;				\

	ld	r10,PACAKMSR(r13) ;				\
@@ -64,7 +63,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ 
	 */

	 */

#define SYSCALL_PSERIES_2_DIRECT				\

#define SYSCALL_PSERIES_2_DIRECT				\

	mflr	r10 ;						\

	mflr	r10 ;						\

	ld	r12,PACAKBASE(r13) ; 				\

	LOAD_HANDLER(r12, system_call_entry) ;			\

	LOAD_HANDLER(r12, system_call_entry) ;			\

	mtctr	r12 ;						\

	mtctr	r12 ;						\

	mfspr	r12,SPRN_SRR1 ;					\

	mfspr	r12,SPRN_SRR1 ;					\
@@ -185,7 +183,6 @@ data_access_slb_pSeries: 
	 * the kernel ends up being put.

	 * the kernel ends up being put.

	 */

	 */

	mfctr	r11

	mfctr	r11

	ld	r10,PACAKBASE(r13)

	LOAD_HANDLER(r10, slb_miss_realmode)

	LOAD_HANDLER(r10, slb_miss_realmode)

	mtctr	r10

	mtctr	r10

	bctr

	bctr
@@ -207,7 +204,6 @@ instruction_access_slb_pSeries: 
	b	slb_miss_realmode

	b	slb_miss_realmode

#else

#else

	mfctr	r11

	mfctr	r11

	ld	r10,PACAKBASE(r13)

	LOAD_HANDLER(r10, slb_miss_realmode)

	LOAD_HANDLER(r10, slb_miss_realmode)

	mtctr	r10

	mtctr	r10

	bctr

	bctr
@@ -459,7 +455,6 @@ BEGIN_FTR_SECTION 
	mfmsr	r11			/* get MSR value */

	mfmsr	r11			/* get MSR value */

	ori	r11,r11,MSR_ME		/* turn on ME bit */

	ori	r11,r11,MSR_ME		/* turn on ME bit */

	ori	r11,r11,MSR_RI		/* turn on RI bit */

	ori	r11,r11,MSR_RI		/* turn on RI bit */

	ld	r12,PACAKBASE(r13)	/* get high part of &label */

	LOAD_HANDLER(r12, machine_check_handle_early)

	LOAD_HANDLER(r12, machine_check_handle_early)

1:	mtspr	SPRN_SRR0,r12

1:	mtspr	SPRN_SRR0,r12

	mtspr	SPRN_SRR1,r11

	mtspr	SPRN_SRR1,r11
@@ -472,7 +467,6 @@ BEGIN_FTR_SECTION 
	 */

	 */

	addi	r1,r1,INT_FRAME_SIZE	/* go back to previous stack frame */

	addi	r1,r1,INT_FRAME_SIZE	/* go back to previous stack frame */

	ld	r11,PACAKMSR(r13)

	ld	r11,PACAKMSR(r13)

	ld	r12,PACAKBASE(r13)

	LOAD_HANDLER(r12, unrecover_mce)

	LOAD_HANDLER(r12, unrecover_mce)

	li	r10,MSR_ME

	li	r10,MSR_ME

	andc	r11,r11,r10		/* Turn off MSR_ME */

	andc	r11,r11,r10		/* Turn off MSR_ME */
@@ -493,7 +487,6 @@ machine_check_pSeries_0: 
	 * used, so nested machine check corrupts it. machine_check_common

	 * used, so nested machine check corrupts it. machine_check_common

	 * enables MSR_RI.

	 * enables MSR_RI.

	 */

	 */

	ld	r12,PACAKBASE(r13)

	ld	r10,PACAKMSR(r13)

	ld	r10,PACAKMSR(r13)

	xori	r10,r10,MSR_RI

	xori	r10,r10,MSR_RI

	mfspr	r11,SPRN_SRR0

	mfspr	r11,SPRN_SRR0
@@ -795,7 +788,6 @@ data_access_slb_relon_pSeries: 
	 * the kernel ends up being put.

	 * the kernel ends up being put.

	 */

	 */

	mfctr	r11

	mfctr	r11

	ld	r10,PACAKBASE(r13)

	LOAD_HANDLER(r10, slb_miss_realmode)

	LOAD_HANDLER(r10, slb_miss_realmode)

	mtctr	r10

	mtctr	r10

	bctr

	bctr
@@ -816,7 +808,6 @@ instruction_access_slb_relon_pSeries: 
	b	slb_miss_realmode

	b	slb_miss_realmode

#else

#else

	mfctr	r11

	mfctr	r11

	ld	r10,PACAKBASE(r13)

	LOAD_HANDLER(r10, slb_miss_realmode)

	LOAD_HANDLER(r10, slb_miss_realmode)

	mtctr	r10

	mtctr	r10

	bctr

	bctr
@@ -1357,7 +1348,6 @@ machine_check_handle_early: 
	andi.	r11,r12,MSR_RI

	andi.	r11,r12,MSR_RI

	bne	2f

	bne	2f

1:	mfspr	r11,SPRN_SRR0

1:	mfspr	r11,SPRN_SRR0

	ld	r10,PACAKBASE(r13)

	LOAD_HANDLER(r10,unrecover_mce)

	LOAD_HANDLER(r10,unrecover_mce)

	mtspr	SPRN_SRR0,r10

	mtspr	SPRN_SRR0,r10

	ld	r10,PACAKMSR(r13)

	ld	r10,PACAKMSR(r13)
@@ -1461,7 +1451,6 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) 
	b	.	/* prevent speculative execution */

	b	.	/* prevent speculative execution */





2:	mfspr	r11,SPRN_SRR0

2:	mfspr	r11,SPRN_SRR0

	ld	r10,PACAKBASE(r13)

	LOAD_HANDLER(r10,unrecov_slb)

	LOAD_HANDLER(r10,unrecov_slb)

	mtspr	SPRN_SRR0,r10

	mtspr	SPRN_SRR0,r10

	ld	r10,PACAKMSR(r13)

	ld	r10,PACAKMSR(r13)
@@ -1478,7 +1467,6 @@ unrecov_slb: 
	b	1b

	b	1b





8:	mfspr	r11,SPRN_SRR0

8:	mfspr	r11,SPRN_SRR0

	ld	r10,PACAKBASE(r13)

	LOAD_HANDLER(r10,bad_addr_slb)

	LOAD_HANDLER(r10,bad_addr_slb)

	mtspr	SPRN_SRR0,r10

	mtspr	SPRN_SRR0,r10

	ld	r10,PACAKMSR(r13)

	ld	r10,PACAKMSR(r13)