Commit d819ce96 authored Nov 27, 2014 by Fabio Estevam Committed by Mark Brown Nov 27, 2014

ASoC: sgtl5000: Remove MCLK restriction

According to the sgtl5000 datasheet the MCLK frequency range restriction of
8 to 27 MHz only applies when the PLL is used - synchronous SYS_MCLK input mode.

When running the codec as slave, the master should generate MCLK in the range of
256*fs, 384*fs or 512*fs, which is called asynchronous SYS_MCLK input mode.

In asynchronous SYS_MCLK we cannot have the 8 to 27 MHz check because if we
want to play a 8KHz sample rate track, with a MCLK of 8k * 512 = 4.096MHz the
current check would return -EINVAL, which is not correct.

Remove the 8 to 27MHz frequency check, since this only applies to the
synchronous SYS_MCLK input case.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

parent ebc01f59

sound/soc/codecs/sgtl5000.c

+0 −9

Original line number	Diff line number	Diff line
		@@ -1435,7 +1435,6 @@ static int sgtl5000_i2c_probe(struct i2c_client *client,
		{
		struct sgtl5000_priv *sgtl5000;
		int ret, reg, rev;
		unsigned int mclk;
		struct device_node *np = client->dev.of_node;
		u32 value;

		@@ -1460,14 +1459,6 @@ static int sgtl5000_i2c_probe(struct i2c_client *client,
		return ret;
		}

		/* SGTL5000 SYS_MCLK should be between 8 and 27 MHz */
		mclk = clk_get_rate(sgtl5000->mclk);
		if (mclk < 8000000 \|\| mclk > 27000000) {
		dev_err(&client->dev, "Invalid SYS_CLK frequency: %u.%03uMHz\n",
		mclk / 1000000, mclk / 1000 % 1000);
		return -EINVAL;
		}

		ret = clk_prepare_enable(sgtl5000->mclk);
		if (ret)
		return ret;