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Commit d7b023d8 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nv94-nvc0/disp: reorder writes to lane current control regs 



Fixes link training issues on some boards.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 687d8f66

drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c

+8 −4
Original line number Diff line number Diff line
@@ -97,8 +97,9 @@ nv94_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp, 
{

	struct nouveau_bios *bios = nouveau_bios(disp);

	struct nv50_disp_priv *priv = (void *)disp;

	const u32 shift = nv94_sor_dp_lane_map(priv, lane);

	const u32 loff = nv94_sor_loff(outp);

	u32 addr, shift = nv94_sor_dp_lane_map(priv, lane);

	u32 addr, data[3];

	u8  ver, hdr, cnt, len;

	struct nvbios_dpout info;

	struct nvbios_dpcfg ocfg;
@@ -113,9 +114,12 @@ nv94_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp, 
	if (!addr)

		return -EINVAL;



	nv_mask(priv, 0x61c118 + loff, 0x000000ff << shift, ocfg.drv << shift);

	nv_mask(priv, 0x61c120 + loff, 0x000000ff << shift, ocfg.pre << shift);

	nv_mask(priv, 0x61c130 + loff, 0x0000ff00, ocfg.unk << 8);

	data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);

	data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);

	data[2] = nv_rd32(priv, 0x61c130 + loff) & ~(0x0000ff00);

	nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.drv << shift));

	nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pre << shift));

	nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.unk << 8));

	return 0;

}