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Commit d71de14d authored by Kenneth Graunke's avatar Kenneth Graunke Committed by Jesse Barnes
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drm/i915: gen7: Disable the RHWO optimization as it can cause GPU hangs. 

The BSpec Workarounds page states that bits 10 and 26 must be set to
avoid 3D ring hangs.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44610


Tested-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarKenneth Graunke <kenneth@whitecape.org>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
parent db099c8f

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -3029,6 +3029,9 @@ 
#define  DISP_FBC_WM_DIS		(1<<15)



/* GEN7 chicken */

#define GEN7_COMMON_SLICE_CHICKEN1		0x7010

# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))



#define GEN7_L3CNTLREG1				0xB01C

#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C

drivers/gpu/drm/i915/intel_display.c

+4 −0
Original line number Diff line number Diff line
@@ -8472,6 +8472,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |

		   CHICKEN3_DGMG_DONE_FIX_DISABLE);



	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */

	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,

		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);



	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */

	I915_WRITE(GEN7_L3CNTLREG1,

			GEN7_WA_FOR_GEN7_L3_CONTROL);