Commit d6feb196 authored Sep 05, 2014 by Ville Syrjälä Committed by Daniel Vetter Sep 19, 2014

drm/i915: Limit the watermark to at least 8 entries on gen2/3

830 is very unhappy of the watermark value is too low (indicating a very
high watermark in fact, ie. memory fetch will occur with an almost full
FIFO). Limit the watermark value to at least 8 cache lines.

That also matches the burst size we use on most platforms. BSpec seems
to indicate we should limit the watermark to 'burst size + 1'. But on
gen4 we already use a hardcoded 8 as the watermark value (as the spec
says we should), so just use 8 as the limit on gen2/3 as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent 1c4e0274

drivers/gpu/drm/i915/intel_pm.c

+11 −0

Original line number	Diff line number	Diff line
		@@ -1070,6 +1070,17 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
		wm_size = wm->max_wm;
		if (wm_size <= 0)
		wm_size = wm->default_wm;

		/*
		* Bspec seems to indicate that the value shouldn't be lower than
		* 'burst size + 1'. Certainly 830 is quite unhappy with low values.
		* Lets go for 8 which is the burst size since certain platforms
		* already use a hardcoded 8 (which is what the spec says should be
		* done).
		*/
		if (wm_size <= 8)
		wm_size = 8;

		return wm_size;
		}