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Commit d6922295 authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/tegra: sor - Do not program interlaced mode registers 



Interlaced mode is currently not supported on the SOR, so don't program
any associated registers.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent a4263fed

drivers/gpu/drm/tegra/sor.c

+0 −3
Original line number Original line Diff line number Diff line
@@ -849,9 +849,6 @@ static int tegra_output_sor_enable(struct tegra_output *output) 
	value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);

	value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);

	tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0));

	tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0));





	/* XXX interlaced mode */

	tegra_sor_writel(sor, 0x00000001, SOR_HEAD_STATE_5(0));



	/* CSTM (LVDS, link A/B, upper) */

	/* CSTM (LVDS, link A/B, upper) */

	value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |

	value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |

		SOR_CSTM_UPPER;

		SOR_CSTM_UPPER;