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Commit d58e0d90 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.19-wip' of git://people.freedesktop.org/~agd5f/linux into drm-next 

- More cursor and hotspot handling fixes
- Fix some typos in the new smc fan control code and enable on CI
- VM and CS cleanups

* 'drm-next-3.19-wip' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: enable smc fan control on CI
  drm/radeon: use pointers instead of indexes for CS chunks
  drm/radeon: remove duplicates check
  drm/ttm: optionally move duplicates to a separate list
  drm/radeon: check the right ring in radeon_evict_flags()
  drm/radeon: fix copy paste typos in fan control for si/ci
  drm/radeon: Hide cursor on CRTCs used by fbdev (v2)
  drm/radeon: add spinlock for BO_VA status protection (v2)
  drm/radeon: fence PT updates as shared
  drm/radeon: rename radeon_cs_reloc to radeon_bo_list
  drm/radeon: drop the handle from radeon_cs_reloc
  drm/radeon drop gobj from radeon_cs_reloc
  drm/radeon: fix typo in new fan control registers for SI/CI
  drm/radeon: sync all BOs involved in a CS
  drm/radeon: Move hotspot handling out of radeon_set_cursor
  drm/radeon: Re-show the cursor after a modeset
parents d5b75dc0 eb8d4d0d

drivers/gpu/drm/qxl/qxl_release.c

+2 −1
Original line number Diff line number Diff line
@@ -264,7 +264,8 @@ int qxl_release_reserve_list(struct qxl_release *release, bool no_intr) 
	if (list_is_singular(&release->bos))

		return 0;



	ret = ttm_eu_reserve_buffers(&release->ticket, &release->bos, !no_intr);

	ret = ttm_eu_reserve_buffers(&release->ticket, &release->bos,

				     !no_intr, NULL);

	if (ret)

		return ret;

drivers/gpu/drm/radeon/atombios_crtc.c

+1 −0
Original line number Diff line number Diff line
@@ -2039,6 +2039,7 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, 
	atombios_crtc_set_base(crtc, x, y, old_fb);

	atombios_overscan_setup(crtc, mode, adjusted_mode);

	atombios_scaler_setup(crtc);

	radeon_cursor_reset(crtc);

	/* update the hw version fpr dpm */

	radeon_crtc->hw_mode = *adjusted_mode;

drivers/gpu/drm/radeon/ci_dpm.c

+3 −4
Original line number Diff line number Diff line
@@ -937,7 +937,7 @@ static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 
	tmp |= TMIN(0);

	WREG32_SMC(CG_FDO_CTRL2, tmp);



	tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;

	tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;

	tmp |= FDO_PWM_MODE(mode);

	WREG32_SMC(CG_FDO_CTRL2, tmp);

}
@@ -1162,7 +1162,7 @@ static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 
	tmp |= TARGET_PERIOD(tach_period);

	WREG32_SMC(CG_TACH_CTRL, tmp);



	ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);

	ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);



	return 0;

}
@@ -1178,7 +1178,7 @@ static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev) 
		tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);

		WREG32_SMC(CG_FDO_CTRL2, tmp);



		tmp = RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK;

		tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;

		tmp |= TMIN(pi->t_min);

		WREG32_SMC(CG_FDO_CTRL2, tmp);

		pi->fan_ctrl_is_in_default_mode = true;
@@ -5849,7 +5849,6 @@ int ci_dpm_init(struct radeon_device *rdev) 
			rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;



	pi->fan_ctrl_is_in_default_mode = true;

	rdev->pm.dpm.fan.ucode_fan_control = false;



	return 0;

}

drivers/gpu/drm/radeon/cikd.h

+4 −4
Original line number Diff line number Diff line
@@ -213,18 +213,18 @@ 


#define	CG_FDO_CTRL0					0xC0300064

#define		FDO_STATIC_DUTY(x)			((x) << 0)

#define		FDO_STATIC_DUTY_MASK			0x0000000F

#define		FDO_STATIC_DUTY_MASK			0x000000FF

#define		FDO_STATIC_DUTY_SHIFT			0

#define	CG_FDO_CTRL1					0xC0300068

#define		FMAX_DUTY100(x)				((x) << 0)

#define		FMAX_DUTY100_MASK			0x0000000F

#define		FMAX_DUTY100_MASK			0x000000FF

#define		FMAX_DUTY100_SHIFT			0

#define	CG_FDO_CTRL2					0xC030006C

#define		TMIN(x)					((x) << 0)

#define		TMIN_MASK				0x0000000F

#define		TMIN_MASK				0x000000FF

#define		TMIN_SHIFT				0

#define		FDO_PWM_MODE(x)				((x) << 11)

#define		FDO_PWM_MODE_MASK			(3 << 11)

#define		FDO_PWM_MODE_MASK			(7 << 11)

#define		FDO_PWM_MODE_SHIFT			11

#define		TACH_PWM_RESP_RATE(x)			((x) << 25)

#define		TACH_PWM_RESP_RATE_MASK			(0x7f << 25)

drivers/gpu/drm/radeon/evergreen_cs.c

+7 −7
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ 
#define MIN(a,b)                   (((a)<(b))?(a):(b))



int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,

			   struct radeon_cs_reloc **cs_reloc);

			   struct radeon_bo_list **cs_reloc);

struct evergreen_cs_track {

	u32			group_size;

	u32			nbanks;
@@ -1094,7 +1094,7 @@ static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p, 
static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)

{

	struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;

	struct radeon_cs_reloc *reloc;

	struct radeon_bo_list *reloc;

	u32 last_reg;

	u32 m, i, tmp, *ib;

	int r;
@@ -1792,7 +1792,7 @@ static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
static int evergreen_packet3_check(struct radeon_cs_parser *p,

				   struct radeon_cs_packet *pkt)

{

	struct radeon_cs_reloc *reloc;

	struct radeon_bo_list *reloc;

	struct evergreen_cs_track *track;

	volatile u32 *ib;

	unsigned idx;
@@ -2661,7 +2661,7 @@ int evergreen_cs_parse(struct radeon_cs_parser *p) 
			p->track = NULL;

			return r;

		}

	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);

	} while (p->idx < p->chunk_ib->length_dw);

#if 0

	for (r = 0; r < p->ib.length_dw; r++) {

		printk(KERN_INFO "%05d  0x%08X\n", r, p->ib.ptr[r]);
@@ -2684,8 +2684,8 @@ int evergreen_cs_parse(struct radeon_cs_parser *p) 
 **/

int evergreen_dma_cs_parse(struct radeon_cs_parser *p)

{

	struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];

	struct radeon_cs_reloc *src_reloc, *dst_reloc, *dst2_reloc;

	struct radeon_cs_chunk *ib_chunk = p->chunk_ib;

	struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc;

	u32 header, cmd, count, sub_cmd;

	volatile u32 *ib = p->ib.ptr;

	u32 idx;
@@ -3100,7 +3100,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) 
			DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);

			return -EINVAL;

		}

	} while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);

	} while (p->idx < p->chunk_ib->length_dw);

#if 0

	for (r = 0; r < p->ib->length_dw; r++) {

		printk(KERN_INFO "%05d  0x%08X\n", r, p->ib.ptr[r]);