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Commit d49316e8 authored by Greg Ungerer's avatar Greg Ungerer
Browse files

m68k: use ColdFire MMU read/write bit flags when ioremapping 



The ColdFire MMU has separate read and write bits, unlike the Motorola
m68k MMU which has a single read-only bit.

Define a _PAGE_READWRITE value for the Motorola MMU, which is 0, so we
can unconditionaly include that in the page table entry bits when setting
up ioremapped pages.

Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
Acked-by: default avatarMatt Waddel <mwaddel@yahoo.com>
Acked-by: default avatarKurt Mahan <kmahan@xmission.com>
Acked-by: default avatarGeert Uytterhoeven <geert@linux-m68k.org>
parent 60610192

arch/m68k/include/asm/motorola_pgtable.h

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#define _PAGE_PRESENT	0x001

#define _PAGE_SHORT	0x002

#define _PAGE_RONLY	0x004

#define _PAGE_READWRITE	0x000

#define _PAGE_ACCESSED	0x008

#define _PAGE_DIRTY	0x010

#define _PAGE_SUPER	0x080	/* 68040 supervisor only */

arch/m68k/mm/kmap.c

+2 −1
Original line number Diff line number Diff line
@@ -171,7 +171,8 @@ void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cachefla 
			break;

		}

	} else {

		physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);

		physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED |

			     _PAGE_DIRTY | _PAGE_READWRITE);

		switch (cacheflag) {

		case IOMAP_NOCACHE_SER:

		case IOMAP_NOCACHE_NONSER: