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Commit d44b4dcb authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter
Browse files

drm/i915: HSW/BDW PSR Set idle_frames = VBT + 1 



Let's use VBT + 1 now we parse it.

v2: fix subject

v3: rebase over intel_psr and without counting on previous fix

Cc: Arthur Runyan <arthur.j.runyan@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarDurgadoss R <durgadoss.r@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent bfd7ebda

drivers/gpu/drm/i915/intel_psr.c

+6 −1
Original line number Diff line number Diff line
@@ -163,7 +163,12 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp) 
	struct drm_device *dev = dig_port->base.base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t max_sleep_time = 0x1f;

	uint32_t idle_frames = 1;

	/* Lately it was identified that depending on panel idle frame count

	 * calculated at HW can be off by 1. So let's use what came

	 * from VBT + 1 and at minimum 2 to be on the safe side.

	 */

	uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ?

			       dev_priv->vbt.psr.idle_frames + 1 : 2;

	uint32_t val = 0x0;

	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;

	bool only_standby = false;