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Commit d3b371cb authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k: Fix regulatory compliance for AR9462/AR9565



Adjust the CCA values based on the regulatory domain
present in the EEPROM.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 3fcdd0a1
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+4 −0
Original line number Diff line number Diff line
@@ -343,8 +343,12 @@

#define AR_PHY_CCA_NOM_VAL_9462_2GHZ          -127
#define AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ     -127
#define AR_PHY_CCA_MAX_GOOD_VAL_9462_2GHZ     -60
#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ -95
#define AR_PHY_CCA_NOM_VAL_9462_5GHZ          -127
#define AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ     -127
#define AR_PHY_CCA_MAX_GOOD_VAL_9462_5GHZ     -60
#define AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ -100

#define AR_PHY_CCA_NOM_VAL_9330_2GHZ          -118

+12 −0
Original line number Diff line number Diff line
@@ -549,6 +549,18 @@ static int ath9k_hw_post_init(struct ath_hw *ah)

	ath9k_hw_ani_init(ah);

	/*
	 * EEPROM needs to be initialized before we do this.
	 * This is required for regulatory compliance.
	 */
	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
		u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
		if ((regdmn & 0xF0) == CTL_FCC) {
			ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ;
			ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ;
		}
	}

	return 0;
}