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Commit d34e210e authored by Gabriel Fernandez's avatar Gabriel Fernandez Committed by Stephen Boyd
Browse files

drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x 



Use a generic name for this kind of PLL

Correction in dts files are already done here:
commit 5eb26c60 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x")

Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 9054a31d

drivers/clk/st/clkgen-fsyn.c

+4 −4
Original line number Diff line number Diff line
@@ -307,7 +307,7 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = { 
	.get_rate	= clk_fs660c32_dig_get_rate,

};



static const struct clkgen_quadfs_data st_fs660c32_C_407 = {

static const struct clkgen_quadfs_data st_fs660c32_C = {

	.nrst_present = true,

	.nrst	= { CLKGEN_FIELD(0x2f0, 0x1, 0),

		    CLKGEN_FIELD(0x2f0, 0x1, 1),
@@ -350,7 +350,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = { 
	.get_rate	= clk_fs660c32_dig_get_rate,

};



static const struct clkgen_quadfs_data st_fs660c32_D_407 = {

static const struct clkgen_quadfs_data st_fs660c32_D = {

	.nrst_present = true,

	.nrst	= { CLKGEN_FIELD(0x2a0, 0x1, 0),

		    CLKGEN_FIELD(0x2a0, 0x1, 1),
@@ -1077,11 +1077,11 @@ static const struct of_device_id quadfs_of_match[] = { 
	},

	{

		.compatible = "st,stih407-quadfs660-C",

		.data = &st_fs660c32_C_407

		.data = &st_fs660c32_C

	},

	{

		.compatible = "st,stih407-quadfs660-D",

		.data = &st_fs660c32_D_407

		.data = &st_fs660c32_D

	},

	{}

};

drivers/clk/st/clkgen-pll.c

+6 −6
Original line number Diff line number Diff line
@@ -193,7 +193,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = { 
	.ops		= &stm_pll3200c32_ops,

};



static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {

static const struct clkgen_pll_data st_pll3200c32_cx_0 = {

	/* 407 C0 PLL0 */

	.pdn_status	= CLKGEN_FIELD(0x2a0,	0x1,			8),

	.locked_status	= CLKGEN_FIELD(0x2a0,	0x1,			24),
@@ -205,7 +205,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = { 
	.ops		= &stm_pll3200c32_ops,

};



static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {

static const struct clkgen_pll_data st_pll3200c32_cx_1 = {

	/* 407 C0 PLL1 */

	.pdn_status	= CLKGEN_FIELD(0x2c8,	0x1,			8),

	.locked_status	= CLKGEN_FIELD(0x2c8,	0x1,			24),
@@ -624,12 +624,12 @@ static const struct of_device_id c32_pll_of_match[] = { 
		.data = &st_pll3200c32_407_a0,

	},

	{

		.compatible = "st,stih407-plls-c32-c0_0",

		.data = &st_pll3200c32_407_c0_0,

		.compatible = "st,plls-c32-cx_0",

		.data = &st_pll3200c32_cx_0,

	},

	{

		.compatible = "st,stih407-plls-c32-c0_1",

		.data = &st_pll3200c32_407_c0_1,

		.compatible = "st,plls-c32-cx_1",

		.data = &st_pll3200c32_cx_1,

	},

	{

		.compatible = "st,stih407-plls-c32-a9",