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Commit d2b4a646 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma

Pull slave-dmaengine updates from Vinod Koul:
 "Once you have some time from extended weekend celebrations please
  consider pulling the following to get:
   - Various fixes and PCI driver for dw_dmac by Andy
   - DT binding for imx-dma by Markus & imx-sdma by Shawn
   - DT fixes for dmaengine by Lars
   - jz4740 dmac driver by Lars
   - and various fixes across the drivers"

What "extended weekend celebrations"?  I'm in the merge window, who has
time for extended celebrations..

* 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (40 commits)
  DMA: shdma: add DT support
  DMA: shdma: shdma_chan_filter() has to be in shdma-base.h
  DMA: shdma: (cosmetic) don't re-calculate a pointer
  dmaengine: at_hdmac: prepare clk before calling enable
  dmaengine/trivial: at_hdmac: add curly brackets to if/else expressions
  dmaengine: at_hdmac: remove unsuded atc_cleanup_descriptors()
  dmaengine: at_hdmac: add FIFO configuration parameter to DMA DT binding
  ARM: at91: dt: add header to define at_hdmac configuration
  MIPS: jz4740: Correct clock gate bit for DMA controller
  MIPS: jz4740: Remove custom DMA API
  MIPS: jz4740: Register jz4740 DMA device
  dma: Add a jz4740 dmaengine driver
  MIPS: jz4740: Acquire and enable DMA controller clock
  dma: mmp_tdma: disable irq when disabling dma channel
  dmaengine: PL08x: Avoid collisions with get_signal() macro
  dmaengine: dw: select DW_DMAC_BIG_ENDIAN_IO automagically
  dma: dw: add PCI part of the driver
  dma: dw: split driver to library part and platform code
  dma: move dw_dmac driver to an own directory
  dw_dmac: don't check resource with devm_ioremap_resource
  ...
parents 8dce5f3d 67eacc15
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+5 −2
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@@ -24,8 +24,11 @@ The three cells in order are:
1. A phandle pointing to the DMA controller.
2. The memory interface (16 most significant bits), the peripheral interface
(16 less significant bits).
3. The peripheral identifier for the hardware handshaking interface. The
3. Parameters for the at91 DMA configuration register which are device
dependant:
  - bit 7-0: peripheral identifier for the hardware handshaking interface. The
  identifier can be different for tx and rx.
  - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 1 for ASAP.

Example:

+48 −0
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* Freescale Direct Memory Access (DMA) Controller for i.MX

This document will only describe differences to the generic DMA Controller and
DMA request bindings as described in dma/dma.txt .

* DMA controller

Required properties:
- compatible : Should be "fsl,<chip>-dma". chip can be imx1, imx21 or imx27
- reg : Should contain DMA registers location and length
- interrupts : First item should be DMA interrupt, second one is optional and
    should contain DMA Error interrupt
- #dma-cells : Has to be 1. imx-dma does not support anything else.

Optional properties:
- #dma-channels : Number of DMA channels supported. Should be 16.
- #dma-requests : Number of DMA requests supported.

Example:

	dma: dma@10001000 {
		compatible = "fsl,imx27-dma";
		reg = <0x10001000 0x1000>;
		interrupts = <32 33>;
		#dma-cells = <1>;
		#dma-channels = <16>;
	};


* DMA client

Clients have to specify the DMA requests with phandles in a list.

Required properties:
- dmas: List of one or more DMA request specifiers. One DMA request specifier
    consists of a phandle to the DMA controller followed by the integer
    specifiying the request line.
- dma-names: List of string identifiers for the DMA requests. For the correct
    names, have a look at the specific client driver.

Example:

	sdhci1: sdhci@10013000 {
		...
		dmas = <&dma 7>;
		dma-names = "rx-tx";
		...
	};
+56 −0
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@@ -4,14 +4,70 @@ Required properties:
- compatible : Should be "fsl,<chip>-sdma"
- reg : Should contain SDMA registers location and length
- interrupts : Should contain SDMA interrupt
- #dma-cells : Must be <3>.
  The first cell specifies the DMA request/event ID.  See details below
  about the second and third cell.
- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
  scripts firmware

The second cell of dma phandle specifies the peripheral type of DMA transfer.
The full ID of peripheral types can be found below.

	ID	transfer type
	---------------------
	0	MCU domain SSI
	1	Shared SSI
	2	MMC
	3	SDHC
	4	MCU domain UART
	5	Shared UART
	6	FIRI
	7	MCU domain CSPI
	8	Shared CSPI
	9	SIM
	10	ATA
	11	CCM
	12	External peripheral
	13	Memory Stick Host Controller
	14	Shared Memory Stick Host Controller
	15	DSP
	16	Memory
	17	FIFO type Memory
	18	SPDIF
	19	IPU Memory
	20	ASRC
	21	ESAI

The third cell specifies the transfer priority as below.

	ID	transfer priority
	-------------------------
	0	High
	1	Medium
	2	Low

Examples:

sdma@83fb0000 {
	compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
	reg = <0x83fb0000 0x4000>;
	interrupts = <6>;
	#dma-cells = <3>;
	fsl,sdma-ram-script-name = "sdma-imx51.bin";
};

DMA clients connected to the i.MX SDMA controller must use the format
described in the dma.txt file.

Examples:

ssi2: ssi@70014000 {
	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
	reg = <0x70014000 0x4000>;
	interrupts = <30>;
	clocks = <&clks 49>;
	dmas = <&sdma 24 1 0>,
	       <&sdma 25 1 0>;
	dma-names = "rx", "tx";
	fsl,fifo-depth = <15>;
};
+75 −0
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* SHDMA Device Tree bindings

Sh-/r-mobile and r-car systems often have multiple identical DMA controller
instances, capable of serving any of a common set of DMA slave devices, using
the same configuration. To describe this topology we require all compatible
SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
DMAC instances have the same number of channels and use the same DMA
descriptors. Therefore respective DMA DT bindings can also all be placed in the
multiplexer node. Even if there is only one such DMAC instance on a system, it
still has to be placed under such a multiplexer node.

* DMA multiplexer

Required properties:
- compatible:	should be "renesas,shdma-mux"
- #dma-cells:	should be <1>, see "dmas" property below

Optional properties (currently unused):
- dma-channels:	number of DMA channels
- dma-requests:	number of DMA request signals

* DMA controller

Required properties:
- compatible:	should be "renesas,shdma"

Example:
	dmac: dma-mux0 {
		compatible = "renesas,shdma-mux";
		#dma-cells = <1>;
		dma-channels = <6>;
		dma-requests = <256>;
		reg = <0 0>;	/* Needed for AUXDATA */
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dma0: shdma@fe008020 {
			compatible = "renesas,shdma";
			reg = <0xfe008020 0x270>,
				<0xfe009000 0xc>;
			interrupt-parent = <&gic>;
			interrupts = <0 34 4
					0 28 4
					0 29 4
					0 30 4
					0 31 4
					0 32 4
					0 33 4>;
			interrupt-names = "error",
					"ch0", "ch1", "ch2", "ch3",
					"ch4", "ch5";
		};

		dma1: shdma@fe018020 {
			...
		};

		dma2: shdma@fe028020 {
			...
		};
	};

* DMA client

Required properties:
- dmas:		a list of <[DMA multiplexer phandle] [MID/RID value]> pairs,
		where MID/RID values are fixed handles, specified in the SoC
		manual
- dma-names:	a list of DMA channel names, one per "dmas" entry

Example:
	dmas = <&dmac 0xd1
		&dmac 0xd2>;
	dma-names = "tx", "rx";
+1 −2
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@@ -7057,8 +7057,7 @@ SYNOPSYS DESIGNWARE DMAC DRIVER
M:	Viresh Kumar <viresh.linux@gmail.com>
S:	Maintained
F:	include/linux/dw_dmac.h
F:	drivers/dma/dw_dmac_regs.h
F:	drivers/dma/dw_dmac.c
F:	drivers/dma/dw/

SYNOPSYS DESIGNWARE MMC/SD/SDIO DRIVER
M:	Seungwon Jeon <tgih.jun@samsung.com>
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