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Commit d131a71c authored by Dong Aisheng's avatar Dong Aisheng Committed by Chris Ball
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mmc: sdhci-esdhc-imx: tuning bits should not be cleared during reset 



We should not clear tuning bits during reset or the SD3.0/eMMC4.5 card
working on UHS mode may not work after reset since the former tuning
settings was lost.

Signed-off-by: default avatarDong Aisheng <b29396@freescale.com>
Acked-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarChris Ball <cjb@laptop.org>
parent d433dc63

drivers/mmc/host/sdhci-esdhc-imx.c

+6 −1
Original line number Diff line number Diff line
@@ -45,6 +45,8 @@ 
#define  ESDHC_MIX_CTRL_FBCLK_SEL	(1 << 25)

/* Bits 3 and 6 are not SDHCI standard definitions */

#define  ESDHC_MIX_CTRL_SDHCI_MASK	0xb7

/* Tuning bits */

#define  ESDHC_MIX_CTRL_TUNING_MASK	0x03c00000



/* dll control register */

#define ESDHC_DLL_CTRL			0x60
@@ -562,7 +564,10 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 
		 * Do it manually here.

		 */

		if (esdhc_is_usdhc(imx_data)) {

			writel(0, host->ioaddr + ESDHC_MIX_CTRL);

			/* the tuning bits should be kept during reset */

			new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);

			writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,

					host->ioaddr + ESDHC_MIX_CTRL);

			imx_data->is_ddr = 0;

		}

	}