Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d0737e1d authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira Committed by Daniel Vetter
Browse files

drm/i915: Make *_crtc_mode_set work on new_config 



This shouldn't change the behavior of those functions, since they are
called after the new_config is made effective and that points to the
current config. In a follow up patch, the mode set sequence will be
changed so this is called before disabling crtcs, and in that case
those functions should work on the staged config.

Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
[danvet: Flatten if by moving the check into the WARN.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent cd0707cb

drivers/gpu/drm/i915/intel_ddi.c

+26 −5
Original line number Diff line number Diff line
@@ -459,6 +459,27 @@ intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 
	return ret;

}



static struct intel_encoder *

intel_ddi_get_crtc_new_encoder(struct intel_crtc *crtc)

{

	struct drm_device *dev = crtc->base.dev;

	struct intel_encoder *intel_encoder, *ret = NULL;

	int num_encoders = 0;



	for_each_intel_encoder(dev, intel_encoder) {

		if (intel_encoder->new_crtc == crtc) {

			ret = intel_encoder;

			num_encoders++;

		}

	}



	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,

	     pipe_name(crtc->pipe));



	BUG_ON(ret == NULL);

	return ret;

}



#define LC_FREQ 2700

#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
@@ -792,7 +813,7 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 
		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |

		      WRPLL_DIVIDER_POST(p);



		intel_crtc->config.dpll_hw_state.wrpll = val;

		intel_crtc->new_config->dpll_hw_state.wrpll = val;



		pll = intel_get_shared_dpll(intel_crtc);

		if (pll == NULL) {
@@ -801,7 +822,7 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 
			return false;

		}



		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);

		intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);

	}



	return true;
@@ -817,9 +838,9 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 
 */

bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)

{

	struct drm_crtc *crtc = &intel_crtc->base;

	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);

	int clock = intel_crtc->config.port_clock;

	struct intel_encoder *intel_encoder =

		intel_ddi_get_crtc_new_encoder(intel_crtc);

	int clock = intel_crtc->new_config->port_clock;



	intel_put_shared_dpll(intel_crtc);

drivers/gpu/drm/i915/intel_display.c

+90 −63
Original line number Diff line number Diff line
@@ -420,13 +420,31 @@ bool intel_pipe_has_type(struct intel_crtc *crtc, int type) 
	return false;

}



/**

 * Returns whether any output on the specified pipe will have the specified

 * type after a staged modeset is complete, i.e., the same as

 * intel_pipe_has_type() but looking at encoder->new_crtc instead of

 * encoder->crtc.

 */

static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)

{

	struct drm_device *dev = crtc->base.dev;

	struct intel_encoder *encoder;



	for_each_intel_encoder(dev, encoder)

		if (encoder->new_crtc == crtc && encoder->type == type)

			return true;



	return false;

}



static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,

						int refclk)

{

	struct drm_device *dev = crtc->base.dev;

	const intel_limit_t *limit;



	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {

		if (intel_is_dual_link_lvds(dev)) {

			if (refclk == 100000)

				limit = &intel_limits_ironlake_dual_lvds_100m;
@@ -449,15 +467,15 @@ static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc) 
	struct drm_device *dev = crtc->base.dev;

	const intel_limit_t *limit;



	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {

		if (intel_is_dual_link_lvds(dev))

			limit = &intel_limits_g4x_dual_channel_lvds;

		else

			limit = &intel_limits_g4x_single_channel_lvds;

	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||

		   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {

	} else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||

		   intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {

		limit = &intel_limits_g4x_hdmi;

	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {

	} else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {

		limit = &intel_limits_g4x_sdvo;

	} else /* The option is for other outputs */

		limit = &intel_limits_i9xx_sdvo;
@@ -475,7 +493,7 @@ static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk) 
	else if (IS_G4X(dev)) {

		limit = intel_g4x_limit(crtc);

	} else if (IS_PINEVIEW(dev)) {

		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))

		if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))

			limit = &intel_limits_pineview_lvds;

		else

			limit = &intel_limits_pineview_sdvo;
@@ -484,14 +502,14 @@ static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk) 
	} else if (IS_VALLEYVIEW(dev)) {

		limit = &intel_limits_vlv;

	} else if (!IS_GEN2(dev)) {

		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))

		if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))

			limit = &intel_limits_i9xx_lvds;

		else

			limit = &intel_limits_i9xx_sdvo;

	} else {

		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))

		if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))

			limit = &intel_limits_i8xx_lvds;

		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))

		else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))

			limit = &intel_limits_i8xx_dvo;

		else

			limit = &intel_limits_i8xx_dac;
@@ -586,7 +604,7 @@ i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, 
	intel_clock_t clock;

	int err = target;



	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {

		/*

		 * For LVDS just rely on its current settings for dual-channel.

		 * We haven't figured out how to reliably set up different
@@ -647,7 +665,7 @@ pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, 
	intel_clock_t clock;

	int err = target;



	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {

		/*

		 * For LVDS just rely on its current settings for dual-channel.

		 * We haven't figured out how to reliably set up different
@@ -710,7 +728,7 @@ g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, 
	int err_most = (target >> 8) + (target >> 9);

	found = false;



	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {

		if (intel_is_dual_link_lvds(dev))

			clock.p2 = limit->p2.p2_fast;

		else
@@ -5628,7 +5646,7 @@ static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors) 


	if (IS_VALLEYVIEW(dev)) {

		refclk = 100000;

	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&

	} else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&

	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {

		refclk = dev_priv->vbt.lvds_ssc_freq;

		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
@@ -6018,29 +6036,29 @@ static void i9xx_update_pll(struct intel_crtc *crtc, 
	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 dpll;

	bool is_sdvo;

	struct dpll *clock = &crtc->config.dpll;

	struct dpll *clock = &crtc->new_config->dpll;



	i9xx_update_pll_dividers(crtc, reduced_clock);



	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||

		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);

	is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||

		intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);



	dpll = DPLL_VGA_MODE_DIS;



	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))

	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))

		dpll |= DPLLB_MODE_LVDS;

	else

		dpll |= DPLLB_MODE_DAC_SERIAL;



	if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {

		dpll |= (crtc->config.pixel_multiplier - 1)

		dpll |= (crtc->new_config->pixel_multiplier - 1)

			<< SDVO_MULTIPLIER_SHIFT_HIRES;

	}



	if (is_sdvo)

		dpll |= DPLL_SDVO_HIGH_SPEED;



	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))

	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DISPLAYPORT))

		dpll |= DPLL_SDVO_HIGH_SPEED;



	/* compute bitmask from p1 value */
@@ -6068,21 +6086,21 @@ static void i9xx_update_pll(struct intel_crtc *crtc, 
	if (INTEL_INFO(dev)->gen >= 4)

		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);



	if (crtc->config.sdvo_tv_clock)

	if (crtc->new_config->sdvo_tv_clock)

		dpll |= PLL_REF_INPUT_TVCLKINBC;

	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&

	else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&

		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)

		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

	else

		dpll |= PLL_REF_INPUT_DREFCLK;



	dpll |= DPLL_VCO_ENABLE;

	crtc->config.dpll_hw_state.dpll = dpll;

	crtc->new_config->dpll_hw_state.dpll = dpll;



	if (INTEL_INFO(dev)->gen >= 4) {

		u32 dpll_md = (crtc->config.pixel_multiplier - 1)

		u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)

			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;

		crtc->config.dpll_hw_state.dpll_md = dpll_md;

		crtc->new_config->dpll_hw_state.dpll_md = dpll_md;

	}

}
@@ -6093,13 +6111,13 @@ static void i8xx_update_pll(struct intel_crtc *crtc, 
	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 dpll;

	struct dpll *clock = &crtc->config.dpll;

	struct dpll *clock = &crtc->new_config->dpll;



	i9xx_update_pll_dividers(crtc, reduced_clock);



	dpll = DPLL_VGA_MODE_DIS;



	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {

		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

	} else {

		if (clock->p1 == 2)
@@ -6110,17 +6128,17 @@ static void i8xx_update_pll(struct intel_crtc *crtc, 
			dpll |= PLL_P2_DIVIDE_BY_4;

	}



	if (!IS_I830(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))

	if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))

		dpll |= DPLL_DVO_2X_MODE;



	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&

	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&

		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)

		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

	else

		dpll |= PLL_REF_INPUT_DREFCLK;



	dpll |= DPLL_VCO_ENABLE;

	crtc->config.dpll_hw_state.dpll = dpll;

	crtc->new_config->dpll_hw_state.dpll = dpll;

}



static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
@@ -6329,7 +6347,10 @@ static int i9xx_crtc_mode_set(struct intel_crtc *crtc, 
	struct intel_encoder *encoder;

	const intel_limit_t *limit;



	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {

	for_each_intel_encoder(dev, encoder) {

		if (encoder->new_crtc != crtc)

			continue;



		switch (encoder->type) {

		case INTEL_OUTPUT_LVDS:

			is_lvds = true;
@@ -6347,7 +6368,7 @@ static int i9xx_crtc_mode_set(struct intel_crtc *crtc, 
	if (is_dsi)

		return 0;



	if (!crtc->config.clock_set) {

	if (!crtc->new_config->clock_set) {

		refclk = i9xx_get_refclk(crtc, num_connectors);



		/*
@@ -6358,7 +6379,7 @@ static int i9xx_crtc_mode_set(struct intel_crtc *crtc, 
		 */

		limit = intel_limit(crtc, refclk);

		ok = dev_priv->display.find_dpll(limit, crtc,

						 crtc->config.port_clock,

						 crtc->new_config->port_clock,

						 refclk, NULL, &clock);

		if (!ok) {

			DRM_ERROR("Couldn't find PLL settings for mode!\n");
@@ -6379,11 +6400,11 @@ static int i9xx_crtc_mode_set(struct intel_crtc *crtc, 
							    &reduced_clock);

		}

		/* Compat-code for transition, will disappear. */

		crtc->config.dpll.n = clock.n;

		crtc->config.dpll.m1 = clock.m1;

		crtc->config.dpll.m2 = clock.m2;

		crtc->config.dpll.p1 = clock.p1;

		crtc->config.dpll.p2 = clock.p2;

		crtc->new_config->dpll.n = clock.n;

		crtc->new_config->dpll.m1 = clock.m1;

		crtc->new_config->dpll.m2 = clock.m2;

		crtc->new_config->dpll.p1 = clock.p1;

		crtc->new_config->dpll.p2 = clock.p2;

	}



	if (IS_GEN2(dev)) {
@@ -6391,9 +6412,9 @@ static int i9xx_crtc_mode_set(struct intel_crtc *crtc, 
				has_reduced_clock ? &reduced_clock : NULL,

				num_connectors);

	} else if (IS_CHERRYVIEW(dev)) {

		chv_update_pll(crtc, &crtc->config);

		chv_update_pll(crtc, crtc->new_config);

	} else if (IS_VALLEYVIEW(dev)) {

		vlv_update_pll(crtc, &crtc->config);

		vlv_update_pll(crtc, crtc->new_config);

	} else {

		i9xx_update_pll(crtc,

				has_reduced_clock ? &reduced_clock : NULL,
@@ -7003,7 +7024,10 @@ static int ironlake_get_refclk(struct drm_crtc *crtc) 
	int num_connectors = 0;

	bool is_lvds = false;



	for_each_encoder_on_crtc(dev, crtc, encoder) {

	for_each_intel_encoder(dev, encoder) {

		if (encoder->new_crtc != to_intel_crtc(crtc))

			continue;



		switch (encoder->type) {

		case INTEL_OUTPUT_LVDS:

			is_lvds = true;
@@ -7194,7 +7218,7 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc, 
	const intel_limit_t *limit;

	bool ret, is_lvds = false;



	is_lvds = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_LVDS);

	is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);



	refclk = ironlake_get_refclk(crtc);
@@ -7205,7 +7229,7 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc, 
	 */

	limit = intel_limit(intel_crtc, refclk);

	ret = dev_priv->display.find_dpll(limit, intel_crtc,

					  intel_crtc->config.port_clock,

					  intel_crtc->new_config->port_clock,

					  refclk, NULL, clock);

	if (!ret)

		return false;
@@ -7255,7 +7279,10 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, 
	int factor, num_connectors = 0;

	bool is_lvds = false, is_sdvo = false;



	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {

	for_each_intel_encoder(dev, intel_encoder) {

		if (intel_encoder->new_crtc != to_intel_crtc(crtc))

			continue;



		switch (intel_encoder->type) {

		case INTEL_OUTPUT_LVDS:

			is_lvds = true;
@@ -7278,10 +7305,10 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, 
		     dev_priv->vbt.lvds_ssc_freq == 100000) ||

		    (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))

			factor = 25;

	} else if (intel_crtc->config.sdvo_tv_clock)

	} else if (intel_crtc->new_config->sdvo_tv_clock)

		factor = 20;



	if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))

	if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))

		*fp |= FP_CB_TUNE;



	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
@@ -7294,20 +7321,20 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, 
	else

		dpll |= DPLLB_MODE_DAC_SERIAL;



	dpll |= (intel_crtc->config.pixel_multiplier - 1)

	dpll |= (intel_crtc->new_config->pixel_multiplier - 1)

		<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;



	if (is_sdvo)

		dpll |= DPLL_SDVO_HIGH_SPEED;

	if (intel_crtc->config.has_dp_encoder)

	if (intel_crtc->new_config->has_dp_encoder)

		dpll |= DPLL_SDVO_HIGH_SPEED;



	/* compute bitmask from p1 value */

	dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

	dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

	/* also FPA1 */

	dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

	dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;



	switch (intel_crtc->config.dpll.p2) {

	switch (intel_crtc->new_config->dpll.p2) {

	case 5:

		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;

		break;
@@ -7348,22 +7375,22 @@ static int ironlake_crtc_mode_set(struct intel_crtc *crtc, 


	ok = ironlake_compute_clocks(&crtc->base, &clock,

				     &has_reduced_clock, &reduced_clock);

	if (!ok && !crtc->config.clock_set) {

	if (!ok && !crtc->new_config->clock_set) {

		DRM_ERROR("Couldn't find PLL settings for mode!\n");

		return -EINVAL;

	}

	/* Compat-code for transition, will disappear. */

	if (!crtc->config.clock_set) {

		crtc->config.dpll.n = clock.n;

		crtc->config.dpll.m1 = clock.m1;

		crtc->config.dpll.m2 = clock.m2;

		crtc->config.dpll.p1 = clock.p1;

		crtc->config.dpll.p2 = clock.p2;

	if (!crtc->new_config->clock_set) {

		crtc->new_config->dpll.n = clock.n;

		crtc->new_config->dpll.m1 = clock.m1;

		crtc->new_config->dpll.m2 = clock.m2;

		crtc->new_config->dpll.p1 = clock.p1;

		crtc->new_config->dpll.p2 = clock.p2;

	}



	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */

	if (crtc->config.has_pch_encoder) {

		fp = i9xx_dpll_compute_fp(&crtc->config.dpll);

	if (crtc->new_config->has_pch_encoder) {

		fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);

		if (has_reduced_clock)

			fp2 = i9xx_dpll_compute_fp(&reduced_clock);
@@ -7371,12 +7398,12 @@ static int ironlake_crtc_mode_set(struct intel_crtc *crtc, 
					     &fp, &reduced_clock,

					     has_reduced_clock ? &fp2 : NULL);



		crtc->config.dpll_hw_state.dpll = dpll;

		crtc->config.dpll_hw_state.fp0 = fp;

		crtc->new_config->dpll_hw_state.dpll = dpll;

		crtc->new_config->dpll_hw_state.fp0 = fp;

		if (has_reduced_clock)

			crtc->config.dpll_hw_state.fp1 = fp2;

			crtc->new_config->dpll_hw_state.fp1 = fp2;

		else

			crtc->config.dpll_hw_state.fp1 = fp;

			crtc->new_config->dpll_hw_state.fp1 = fp;



		pll = intel_get_shared_dpll(crtc);

		if (pll == NULL) {