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Commit d060c169 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
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drm/i915: Reorganize the overclock code 



The existing code (which I changed last) was very convoluted. I believe
it was attempting to skip the overclock portion if the previous pcode
write failed. When I last touched the code, I was preserving this
behavior. There is some benefit to doing it that way in that if the
first pcode access fails, the later is likely invalid.

Having a bit more confidence in my understanding of how things work, I
now feel it's better to have clear, readable, code than to try to skip
over this one operation in an unusual case.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 33688d95

drivers/gpu/drm/i915/intel_pm.c

+9 −11
Original line number Diff line number Diff line
@@ -3326,7 +3326,7 @@ static void gen6_enable_rps(struct drm_device *dev) 
	struct intel_ring_buffer *ring;

	u32 rp_state_cap, hw_max, hw_min;

	u32 gt_perf_status;

	u32 rc6vids, pcu_mbox, rc6_mask = 0;

	u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;

	u32 gtfifodbg;

	int rc6_mode;

	int i, ret;
@@ -3414,8 +3414,9 @@ static void gen6_enable_rps(struct drm_device *dev) 
	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);



	ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);

	if (!ret) {

		pcu_mbox = 0;

	if (ret)

		DRM_DEBUG_DRIVER("Failed to set the min frequency\n");



	ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);

	if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */

		DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
@@ -3423,9 +3424,6 @@ static void gen6_enable_rps(struct drm_device *dev) 
				 (pcu_mbox & 0xff) * 50);

		dev_priv->rps.hw_max = pcu_mbox & 0xff;

	}

	} else {

		DRM_DEBUG_DRIVER("Failed to set the min frequency\n");

	}



	dev_priv->rps.power = HIGH_POWER; /* force a reset */

	gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);