Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d00a5692 authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Ingo Molnar
Browse files

arch,x86: Convert smp_mb__*() 



x86 is strongly ordered and all its atomic ops imply a full barrier.

Implement the two new primitives as the old ones were.

Signed-off-by: default avatarPeter Zijlstra <peterz@infradead.org>
Acked-by: default avatarPaul E. McKenney <paulmck@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-knswsr5mldkr0w1lrdxvc81w@git.kernel.org


Cc: Dave Jones <davej@redhat.com>
Cc: Jesse Brandeburg <jesse.brandeburg@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Michel Lespinasse <walken@google.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent ce3609f9

arch/x86/include/asm/atomic.h

+1 −6
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include <asm/alternative.h>

#include <asm/cmpxchg.h>

#include <asm/rmwcc.h>

#include <asm/barrier.h>



/*

 * Atomic operations that C can't guarantee us.  Useful for
@@ -243,12 +244,6 @@ static inline void atomic_or_long(unsigned long *v1, unsigned long v2) 
		     : : "r" ((unsigned)(mask)), "m" (*(addr))	\

		     : "memory")



/* Atomic operations are already serializing on x86 */

#define smp_mb__before_atomic_dec()	barrier()

#define smp_mb__after_atomic_dec()	barrier()

#define smp_mb__before_atomic_inc()	barrier()

#define smp_mb__after_atomic_inc()	barrier()



#ifdef CONFIG_X86_32

# include <asm/atomic64_32.h>

#else

arch/x86/include/asm/barrier.h

+4 −0
Original line number Diff line number Diff line
@@ -137,6 +137,10 @@ do { \ 


#endif



/* Atomic operations are already serializing on x86 */

#define smp_mb__before_atomic()	barrier()

#define smp_mb__after_atomic()	barrier()



/*

 * Stop RDTSC speculation. This is needed when you need to use RDTSC

 * (or get_cycles or vread that possibly accesses the TSC) in a defined

arch/x86/include/asm/bitops.h

+2 −4
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/compiler.h>

#include <asm/alternative.h>

#include <asm/rmwcc.h>

#include <asm/barrier.h>



#if BITS_PER_LONG == 32

# define _BITOPS_LONG_SHIFT 5
@@ -102,7 +103,7 @@ static inline void __set_bit(long nr, volatile unsigned long *addr) 
 *

 * clear_bit() is atomic and may not be reordered.  However, it does

 * not contain a memory barrier, so if it is used for locking purposes,

 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()

 * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()

 * in order to ensure changes are visible on other processors.

 */

static __always_inline void
@@ -156,9 +157,6 @@ static inline void __clear_bit_unlock(long nr, volatile unsigned long *addr) 
	__clear_bit(nr, addr);

}



#define smp_mb__before_clear_bit()	barrier()

#define smp_mb__after_clear_bit()	barrier()



/**

 * __change_bit - Toggle a bit in memory

 * @nr: the bit to change

arch/x86/include/asm/sync_bitops.h

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ static inline void sync_set_bit(long nr, volatile unsigned long *addr) 
 *

 * sync_clear_bit() is atomic and may not be reordered.  However, it does

 * not contain a memory barrier, so if it is used for locking purposes,

 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()

 * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()

 * in order to ensure changes are visible on other processors.

 */

static inline void sync_clear_bit(long nr, volatile unsigned long *addr)

arch/x86/kernel/apic/hw_nmi.c

+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ void arch_trigger_all_cpu_backtrace(void) 
	}



	clear_bit(0, &backtrace_flag);

	smp_mb__after_clear_bit();

	smp_mb__after_atomic();

}



static int __kprobes