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Commit cf5d3180 authored by Stephen Warren's avatar Stephen Warren Committed by Bjorn Helgaas
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PCI: tegra: Program PADS_REFCLK_CFG* always, not just on legacy SoCs 



tegra_pcie_phy_power_on() calls tegra_pcie_phy_enable() only for legacy
SoCs.  However, part of tegra_pcie_phy_enable() needs to happen in all
cases.  Move that code up one level into tegra_pcie_phy_power_on().

[bhelgaas: changelog]
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
parent 08203f1f

drivers/pci/host/pci-tegra.c

+9 −6
Original line number Original line Diff line number Diff line
@@ -838,12 +838,6 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) 
	value |= PADS_PLL_CTL_RST_B4SM;

	value |= PADS_PLL_CTL_RST_B4SM;

	pads_writel(pcie, value, soc->pads_pll_ctl);

	pads_writel(pcie, value, soc->pads_pll_ctl);





	/* Configure the reference clock driver */

	value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);

	pads_writel(pcie, value, PADS_REFCLK_CFG0);

	if (soc->num_ports > 2)

		pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);



	/* wait for the PLL to lock */

	/* wait for the PLL to lock */

	err = tegra_pcie_pll_wait(pcie, 500);

	err = tegra_pcie_pll_wait(pcie, 500);

	if (err < 0) {

	if (err < 0) {
@@ -927,7 +921,9 @@ static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port) 




static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)

static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)

{

{

	const struct tegra_pcie_soc_data *soc = pcie->soc_data;

	struct tegra_pcie_port *port;

	struct tegra_pcie_port *port;

	u32 value;

	int err;

	int err;





	if (pcie->legacy_phy) {

	if (pcie->legacy_phy) {
@@ -952,6 +948,13 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) 
		}

		}

	}

	}





	/* Configure the reference clock driver */

	value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);

	pads_writel(pcie, value, PADS_REFCLK_CFG0);



	if (soc->num_ports > 2)

		pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);



	return 0;

	return 0;

}

}