ARM i.MX6Q: Fix IOMUXC GPR1 defines for ENET_CLK_SEL and IPU1/2_MUX

#define IMX6Q_GPR1_EXC_MON_MASK			BIT(22)

#define IMX6Q_GPR1_EXC_MON_OKAY			0x0

#define IMX6Q_GPR1_EXC_MON_SLVE			BIT(22)

#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK		BIT(21)

#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET		0x0

#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX		BIT(21)

#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK		BIT(20)

#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET		0x0

#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(20)

#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK		BIT(19)

#define IMX6Q_GPR1_ENET_CLK_SEL_MASK		BIT(21)

#define IMX6Q_GPR1_ENET_CLK_SEL_PAD		0

#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP		BIT(21)

#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK		BIT(20)

#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET		0x0

#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(19)

#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(20)

#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK		BIT(19)

#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET		0x0

#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(19)

#define IMX6Q_GPR1_PCIE_TEST_PD			BIT(18)

#define IMX6Q_GPR1_IPU_VPU_MUX_MASK		BIT(17)

#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1		0x0