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Commit ce61966c authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Stephen Boyd
Browse files

clk: gcc-msm8996: Fix pcie 2 pipe register offset 



This patch corrects the register offset for pcie2 pipe clock.
Offset according to datasheet is 0x6e018 instead of 0x6e108.

Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: b1e010c0 ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver")
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 6d91f2c0

drivers/clk/qcom/gcc-msm8996.c

+2 −2
Original line number Diff line number Diff line
@@ -2592,9 +2592,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = { 
};



static struct clk_branch gcc_pcie_2_pipe_clk = {

	.halt_reg = 0x6e108,

	.halt_reg = 0x6e018,

	.clkr = {

		.enable_reg = 0x6e108,

		.enable_reg = 0x6e018,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_2_pipe_clk",