Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ce43a216 authored by Bruce Allan's avatar Bruce Allan Committed by Jeff Kirsher
Browse files

e1000e: cleanup USLEEP_RANGE checkpatch checks 



Resolve strict checkpatch USLEEP_RANGE checks by converting delays and
sleeps as described in ./Documentation/timers/timers-howto.txt.  Three
other violations of the text have also been fixed.

CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see
Documentation/timers/timers-howto.txt

Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent e5fe2541

drivers/net/ethernet/intel/e1000e/80003es2lan.c

+6 −6
Original line number Diff line number Diff line
@@ -395,7 +395,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 
		 * before the device has completed the "Page Select" MDI

		 * transaction.  So we wait 200us after each MDI command...

		 */

		udelay(200);

		usleep_range(200, 400);



		/* ...and verify the command was successful. */

		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
@@ -405,13 +405,13 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 
			return -E1000_ERR_PHY;

		}



		udelay(200);

		usleep_range(200, 400);



		ret_val = e1000e_read_phy_reg_mdic(hw,

						   MAX_PHY_REG_ADDRESS & offset,

						   data);



		udelay(200);

		usleep_range(200, 400);

	} else {

		ret_val = e1000e_read_phy_reg_mdic(hw,

						   MAX_PHY_REG_ADDRESS & offset,
@@ -464,7 +464,7 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 
		 * before the device has completed the "Page Select" MDI

		 * transaction.  So we wait 200us after each MDI command...

		 */

		udelay(200);

		usleep_range(200, 400);



		/* ...and verify the command was successful. */

		ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
@@ -474,13 +474,13 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 
			return -E1000_ERR_PHY;

		}



		udelay(200);

		usleep_range(200, 400);



		ret_val = e1000e_write_phy_reg_mdic(hw,

						    MAX_PHY_REG_ADDRESS &

						    offset, data);



		udelay(200);

		usleep_range(200, 400);

	} else {

		ret_val = e1000e_write_phy_reg_mdic(hw,

						    MAX_PHY_REG_ADDRESS &

drivers/net/ethernet/intel/e1000e/82571.c

+6 −6
Original line number Diff line number Diff line
@@ -437,7 +437,7 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 
			return ret_val;



		phy->id = (u32)(phy_id << 16);

		udelay(20);

		usleep_range(20, 40);

		ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);

		if (ret_val)

			return ret_val;
@@ -482,7 +482,7 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 
		if (!(swsm & E1000_SWSM_SMBI))

			break;



		udelay(50);

		usleep_range(50, 100);

		i++;

	}
@@ -499,7 +499,7 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 
		if (er32(SWSM) & E1000_SWSM_SWESMBI)

			break;



		udelay(50);

		usleep_range(50, 100);

	}



	if (i == fw_timeout) {
@@ -1022,7 +1022,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 
	}



	if (hw->nvm.type == e1000_nvm_flash_hw) {

		udelay(10);

		usleep_range(10, 20);

		ctrl_ext = er32(CTRL_EXT);

		ctrl_ext |= E1000_CTRL_EXT_EE_RST;

		ew32(CTRL_EXT, ctrl_ext);
@@ -1529,7 +1529,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 
	status = er32(STATUS);

	er32(RXCW);

	/* SYNCH bit and IV bit are sticky */

	udelay(10);

	usleep_range(10, 20);

	rxcw = er32(RXCW);



	if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
@@ -1632,7 +1632,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) 
			 * the IV bit and restart Autoneg

			 */

			for (i = 0; i < AN_RETRY_COUNT; i++) {

				udelay(10);

				usleep_range(10, 20);

				rxcw = er32(RXCW);

				if ((rxcw & E1000_RXCW_SYNCH) &&

				    (rxcw & E1000_RXCW_C))

drivers/net/ethernet/intel/e1000e/e1000.h

+1 −1
Original line number Diff line number Diff line
@@ -597,7 +597,7 @@ static inline s32 __ew32_prepare(struct e1000_hw *hw) 
	s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;



	while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)

		udelay(50);

		usleep_range(50, 100);



	return i;

}

drivers/net/ethernet/intel/e1000e/ethtool.c

+5 −5
Original line number Diff line number Diff line
@@ -1297,7 +1297,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter) 


		ew32(CTRL, ctrl_reg);

		e1e_flush();

		udelay(500);

		usleep_range(500, 1000);



		return 0;

	}
@@ -1323,7 +1323,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter) 
		e1e_wphy(hw, PHY_REG(2, 21), phy_reg);

		/* Assert SW reset for above settings to take effect */

		hw->phy.ops.commit(hw);

		mdelay(1);

		usleep_range(1000, 2000);

		/* Force Full Duplex */

		e1e_rphy(hw, PHY_REG(769, 16), &phy_reg);

		e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C);
@@ -1364,7 +1364,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter) 


	/* force 1000, set loopback */

	e1e_wphy(hw, MII_BMCR, 0x4140);

	mdelay(250);

	msleep(250);



	/* Now set up the MAC to the same speed/duplex as the PHY. */

	ctrl_reg = er32(CTRL);
@@ -1396,7 +1396,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter) 
	if (hw->phy.type == e1000_phy_m88)

		e1000_phy_disable_receiver(adapter);



	udelay(500);

	usleep_range(500, 1000);



	return 0;

}
@@ -1704,7 +1704,7 @@ static int e1000_link_test(struct e1000_adapter *adapter, u64 *data) 
			/* On some Phy/switch combinations, link establishment

			 * can take a few seconds more than expected.

			 */

			msleep(5000);

			msleep_interruptible(5000);



		if (!(er32(STATUS) & E1000_STATUS_LU))

			*data = 1;

drivers/net/ethernet/intel/e1000e/ich8lan.c

+8 −8
Original line number Diff line number Diff line
@@ -312,7 +312,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 
		mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;

		ew32(CTRL, mac_reg);

		e1e_flush();

		udelay(10);

		usleep_range(10, 20);

		mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;

		ew32(CTRL, mac_reg);

		e1e_flush();
@@ -1517,7 +1517,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 
	if (ret_val)

		return ret_val;



	udelay(20);

	usleep_range(20, 40);

	ctrl_ext = er32(CTRL_EXT);

	ctrl_reg = er32(CTRL);
@@ -1527,11 +1527,11 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 


	ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);

	e1e_flush();

	udelay(20);

	usleep_range(20, 40);

	ew32(CTRL, ctrl_reg);

	ew32(CTRL_EXT, ctrl_ext);

	e1e_flush();

	udelay(20);

	usleep_range(20, 40);



	return 0;

}
@@ -2037,7 +2037,7 @@ static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 
	do {

		data = er32(STATUS);

		data &= E1000_STATUS_LAN_INIT_DONE;

		udelay(100);

		usleep_range(100, 200);

	} while ((!data) && --loop);



	/* If basic configuration is incomplete before the above loop
@@ -2801,7 +2801,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 
		/* Convert offset to bytes. */

		act_offset = (i + new_bank_offset) << 1;



		udelay(100);

		usleep_range(100, 200);

		/* Write the bytes to the new bank. */

		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,

							       act_offset,
@@ -2809,7 +2809,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 
		if (ret_val)

			break;



		udelay(100);

		usleep_range(100, 200);

		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,

							       act_offset + 1,

							       (u8)(data >> 8));
@@ -3077,7 +3077,7 @@ static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 


	for (program_retries = 0; program_retries < 100; program_retries++) {

		e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);

		udelay(100);

		usleep_range(100, 200);

		ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);

		if (!ret_val)

			break;