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Commit ce0c9821 authored by Shashank Sharma's avatar Shashank Sharma Committed by Daniel Vetter
Browse files

drm/i915/bxt: get DSI pixelclock 



BXT's DSI PLL is different from that of VLV. So this patch
adds a new function to get the current DSI pixel clock based
on the PLL divider ratio and lane count.

This function is required for intel_dsi_get_config() function.

v2: Fixed Jani's review comments.

Signed-off-by: default avatarShashank Sharma <shashank.sharma@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent baeac68a

drivers/gpu/drm/i915/intel_dsi.c

+6 −2
Original line number Diff line number Diff line
@@ -695,7 +695,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 
static void intel_dsi_get_config(struct intel_encoder *encoder,

				 struct intel_crtc_state *pipe_config)

{

	u32 pclk;

	u32 pclk = 0;

	DRM_DEBUG_KMS("\n");



	/*
@@ -704,7 +704,11 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, 
	 */

	pipe_config->dpll_hw_state.dpll_md = 0;



	if (IS_BROXTON(encoder->base.dev))

		pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);

	else if (IS_VALLEYVIEW(encoder->base.dev))

		pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);



	if (!pclk)

		return;

drivers/gpu/drm/i915/intel_dsi.h

+1 −0
Original line number Diff line number Diff line
@@ -127,6 +127,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) 
extern void intel_enable_dsi_pll(struct intel_encoder *encoder);

extern void intel_disable_dsi_pll(struct intel_encoder *encoder);

extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);

extern u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);

extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,

							enum port port);

drivers/gpu/drm/i915/intel_dsi_pll.c

+35 −0
Original line number Diff line number Diff line
@@ -384,6 +384,41 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) 
	return pclk;

}



u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)

{

	u32 pclk;

	u32 dsi_clk;

	u32 dsi_ratio;

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;



	/* Divide by zero */

	if (!pipe_bpp) {

		DRM_ERROR("Invalid BPP(0)\n");

		return 0;

	}



	dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &

				BXT_DSI_PLL_RATIO_MASK;



	/* Invalid DSI ratio ? */

	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||

			dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {

		DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);

		return 0;

	}



	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;



	/* pixel_format and pipe_bpp should agree */

	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);



	pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);



	DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);

	return pclk;

}



void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)

{

	u32 temp;