Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cdfe3175 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'mvebu-pinctrl-3.15' of git://git.infradead.org/linux-mvebu into pinctrl-mvebu 

mvebu pinctrl changes for v3.15

 - various cleanup and refactorization
 - add drivers for the Armada 375, 380, and 385 SoCs
 - prepare dove for SoC code moving into mach-mvebu
 - DT documentation updates
parents 38dbfb59 7cab36e5

Documentation/devicetree/bindings/arm/marvell,dove.txt

0 → 100644
+22 −0
Original line number Diff line number Diff line 
Marvell Dove Platforms Device Tree Bindings

-----------------------------------------------



Boards with a Marvell Dove SoC shall have the following properties:



Required root node property:

- compatible: must contain "marvell,dove";



* Global Configuration registers



Global Configuration registers of Dove SoC are shared by a syscon node.



Required properties:

- compatible: must contain "marvell,dove-global-config" and "syscon".

- reg: base address and size of the Global Configuration registers.



Example:



gconf: global-config@e802c {

	compatible = "marvell,dove-global-config", "syscon";

	reg = <0xe802c 0x14>;

};

Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ part and usage. 


Required properties:

- compatible: "marvell,88f6710-pinctrl"

- reg: register specifier of MPP registers



Available mpp pins/groups and functions:

Note: brackets (x) are not part of the mpp name for marvell,function and given

Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt

0 → 100644
+82 −0
Original line number Diff line number Diff line 
* Marvell Armada 375 SoC pinctrl driver for mpp



Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding

part and usage.



Required properties:

- compatible: "marvell,88f6720-pinctrl"

- reg: register specifier of MPP registers



Available mpp pins/groups and functions:

Note: brackets (x) are not part of the mpp name for marvell,function and given

only for more detailed description in this document.



name          pins     functions

================================================================================

mpp0          0        gpio, dev(ad2), spi0(cs1), spi1(cs1)

mpp1          1        gpio, dev(ad3), spi0(mosi), spi1(mosi)

mpp2          2        gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi)

mpp3          3        gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk)

mpp4          4        gpio, dev(ad6), spi0(miso), spi1(miso)

mpp5          5        gpio, dev(ad7), spi0(cs2), spi1(cs2)

mpp6          6        gpio, dev(ad0), led(p1), audio(rclk)

mpp7          7        gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)

mpp8          8        gpio, dev (bootcs), spi0(cs0), spi1(cs0)

mpp9          9        gpio, nf(wen), spi0(sck), spi1(sck)

mpp10        10        gpio, nf(ren), dram(vttctrl), led(c1)

mpp11        11        gpio, dev(a0), led(c2), audio(sdo)

mpp12        12        gpio, dev(a1), audio(bclk)

mpp13        13        gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)

mpp14        14        gpio, i2c0(sda), uart1(txd)

mpp15        15        gpio, i2c0(sck), uart1(rxd)

mpp16        16        gpio, uart0(txd)

mpp17        17        gpio, uart0(rxd)

mpp18        18        gpio, tdm(intn)

mpp19        19        gpio, tdm(rstn)

mpp20        20        gpio, tdm(pclk)

mpp21        21        gpio, tdm(fsync)

mpp22        22        gpio, tdm(drx)

mpp23        23        gpio, tdm(dtx)

mpp24        24        gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts)

mpp25        25        gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts)

mpp26        26        gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts)

mpp27        27        gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts)

mpp28        28        gpio, led(p3), ge1(txctl), sd(clk)

mpp29        29        gpio, pcie1(clkreq), ge1(rxclk), sd(d3)

mpp30        30        gpio, ge1(txd0), spi1(cs0)

mpp31        31        gpio, ge1(txd1), spi1(mosi)

mpp32        32        gpio, ge1(txd2), spi1(sck), ptp(triggen)

mpp33        33        gpio, ge1(txd3), spi1(miso)

mpp34        34        gpio, ge1(txclkout), spi1(sck)

mpp35        35        gpio, ge1(rxctl), spi1(cs1), spi0(cs2)

mpp36        36        gpio, pcie0(clkreq)

mpp37        37        gpio, pcie0(clkreq), tdm(intn), ge(mdc)

mpp38        38        gpio, pcie1(clkreq), ge(mdio)

mpp39        39        gpio, ref(clkout)

mpp40        40        gpio, uart1(txd)

mpp41        41        gpio, uart1(rxd)

mpp42        42        gpio, spi1(cs2), led(c0)

mpp43        43        gpio, sata0(prsnt), dram(vttctrl)

mpp44        44        gpio, sata0(prsnt)

mpp45        45        gpio, spi0(cs2), pcie0(rstoutn)

mpp46        46        gpio, led(p0), ge0(txd0), ge1(txd0)

mpp47        47        gpio, led(p1), ge0(txd1), ge1(txd1)

mpp48        48        gpio, led(p2), ge0(txd2), ge1(txd2)

mpp49        49        gpio, led(p3), ge0(txd3), ge1(txd3)

mpp50        50        gpio, led(c0), ge0(rxd0), ge1(rxd0)

mpp51        51        gpio, led(c1), ge0(rxd1), ge1(rxd1)

mpp52        52        gpio, led(c2), ge0(rxd2), ge1(rxd2)

mpp53        53        gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3)

mpp54        54        gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl)

mpp55        55        gpio, ge0(rxclk), ge1(rxclk)

mpp56        56        gpio, ge0(txclkout), ge1(txclkout)

mpp57        57        gpio, ge0(txctl), ge1(txctl)

mpp58        58        gpio, led(c0)

mpp59        59        gpio, led(c1)

mpp60        60        gpio, uart1(txd), led(c2)

mpp61        61        gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)

mpp62        62        gpio, i2c1(sck), led(p1)

mpp63        63        gpio, ptp(triggen), led(p2)

mpp64        64        gpio, dram(vttctrl), led(p3)

mpp65        65        gpio, sata1(prsnt)

mpp66        66        gpio, ptp(eventreq), spi1(cs3)

Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt

0 → 100644
+80 −0
Original line number Diff line number Diff line 
* Marvell Armada 380/385 SoC pinctrl driver for mpp



Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding

part and usage.



Required properties:

- compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or

  "marvell,88f6828-pinctrl" depending on the specific variant of the

  SoC being used.

- reg: register specifier of MPP registers



Available mpp pins/groups and functions:

Note: brackets (x) are not part of the mpp name for marvell,function and given

only for more detailed description in this document.



name          pins     functions

================================================================================

mpp0          0        gpio, ua0(rxd)

mpp1          1        gpio, ua0(txd)

mpp2          2        gpio, i2c0(sck)

mpp3          3        gpio, i2c0(sda)

mpp4          4        gpio, ge(mdc), ua1(txd), ua0(rts)

mpp5          5        gpio, ge(mdio), ua1(rxd), ua0(cts)

mpp6          6        gpio, ge0(txclkout), ge0(crs), dev(cs3)

mpp7          7        gpio, ge0(txd0), dev(ad9)

mpp8          8        gpio, ge0(txd1), dev(ad10)

mpp9          9        gpio, ge0(txd2), dev(ad11)

mpp10         10       gpio, ge0(txd3), dev(ad12)

mpp11         11       gpio, ge0(txctl), dev(ad13)

mpp12         12       gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14)

mpp13         13       gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15)

mpp14         14       gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1)

mpp15         15       gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1]

mpp16         16       gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq)

mpp17         17       gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt)

mpp18         18       gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1]

mpp19         19       gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts)

mpp20         20       gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts)

mpp21         21       gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs)

mpp22         22       gpio, spi0(mosi), dev(ad0)

mpp23         23       gpio, spi0(sck), dev(ad2)

mpp24         24       gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)

mpp25         25       gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)

mpp26         26       gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)

mpp27         27       gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2)

mpp28         28       gpio, ge1(txd0), sd0(clk), dev(ad5)

mpp29         29       gpio, ge1(txd1), dev(ale0)

mpp30         30       gpio, ge1(txd2), dev(oen)

mpp31         31       gpio, ge1(txd3), dev(ale1)

mpp32         32       gpio, ge1(txctl), dev(wen0)

mpp33         33       gpio, m(decc_err), dev(ad3)

mpp34         34       gpio, dev(ad1)

mpp35         35       gpio, ref(clk_out1), dev(a1)

mpp36         36       gpio, ptp(trig_gen), dev(a0)

mpp37         37       gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8)

mpp38         38       gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)

mpp39         39       gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2)

mpp40         40       gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6)

mpp41         41       gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last)

mpp42         42       gpio, ua1(txd), ua0(rts), dev(ad7)

mpp43         43       gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout)

mpp44         44       gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout)

mpp45         45       gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)

mpp46         46       gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)

mpp47         47       gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2]

mpp48         48       gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4)

mpp49         49       gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5)

mpp50         50       gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd)

mpp51         51       gpio, tdm2c(dtx), audio(sdo), m(decc_err)

mpp52         52       gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6)

mpp53         53       gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7)

mpp54         54       gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3)

mpp55         55       gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0)

mpp56         56       gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi)

mpp57         57       gpio, spi1(sck), sd0(clk)

mpp58         58       gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1)

mpp59         59       gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2)



[1]: only available on 88F6820 and 88F6828

[2]: only available on 88F6828

Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ part and usage. 
Required properties:

- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",

              "marvell,mv78460-pinctrl"

- reg: register specifier of MPP registers



This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.