Loading arch/arm/boot/dts/emev2.dtsi +48 −0 Original line number Diff line number Diff line Loading @@ -21,6 +21,8 @@ gpio2 = &gpio2; gpio3 = &gpio3; gpio4 = &gpio4; i2c0 = &iic0; i2c1 = &iic1; }; cpus { Loading Loading @@ -66,6 +68,30 @@ clock-frequency = <32768>; #clock-cells = <0>; }; iic0_sclkdiv: iic0_sclkdiv { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x624 0>; clocks = <&pll3_fo>; #clock-cells = <0>; }; iic0_sclk: iic0_sclk { compatible = "renesas,emev2-smu-gclk"; reg = <0x48c 1>; clocks = <&iic0_sclkdiv>; #clock-cells = <0>; }; iic1_sclkdiv: iic1_sclkdiv { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x624 16>; clocks = <&pll3_fo>; #clock-cells = <0>; }; iic1_sclk: iic1_sclk { compatible = "renesas,emev2-smu-gclk"; reg = <0x490 1>; clocks = <&iic1_sclkdiv>; #clock-cells = <0>; }; pll3_fo: pll3_fo { compatible = "fixed-factor-clock"; clocks = <&c32ki>; Loading Loading @@ -234,4 +260,26 @@ interrupt-controller; #interrupt-cells = <2>; }; iic0: i2c@e0070000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-emev2"; reg = <0xe0070000 0x28>; interrupts = <0 32 IRQ_TYPE_EDGE_RISING>; clocks = <&iic0_sclk>; clock-names = "sclk"; status = "disabled"; }; iic1: i2c@e10a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-emev2"; reg = <0xe10a0000 0x28>; interrupts = <0 33 IRQ_TYPE_EDGE_RISING>; clocks = <&iic1_sclk>; clock-names = "sclk"; status = "disabled"; }; }; Loading
arch/arm/boot/dts/emev2.dtsi +48 −0 Original line number Diff line number Diff line Loading @@ -21,6 +21,8 @@ gpio2 = &gpio2; gpio3 = &gpio3; gpio4 = &gpio4; i2c0 = &iic0; i2c1 = &iic1; }; cpus { Loading Loading @@ -66,6 +68,30 @@ clock-frequency = <32768>; #clock-cells = <0>; }; iic0_sclkdiv: iic0_sclkdiv { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x624 0>; clocks = <&pll3_fo>; #clock-cells = <0>; }; iic0_sclk: iic0_sclk { compatible = "renesas,emev2-smu-gclk"; reg = <0x48c 1>; clocks = <&iic0_sclkdiv>; #clock-cells = <0>; }; iic1_sclkdiv: iic1_sclkdiv { compatible = "renesas,emev2-smu-clkdiv"; reg = <0x624 16>; clocks = <&pll3_fo>; #clock-cells = <0>; }; iic1_sclk: iic1_sclk { compatible = "renesas,emev2-smu-gclk"; reg = <0x490 1>; clocks = <&iic1_sclkdiv>; #clock-cells = <0>; }; pll3_fo: pll3_fo { compatible = "fixed-factor-clock"; clocks = <&c32ki>; Loading Loading @@ -234,4 +260,26 @@ interrupt-controller; #interrupt-cells = <2>; }; iic0: i2c@e0070000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-emev2"; reg = <0xe0070000 0x28>; interrupts = <0 32 IRQ_TYPE_EDGE_RISING>; clocks = <&iic0_sclk>; clock-names = "sclk"; status = "disabled"; }; iic1: i2c@e10a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-emev2"; reg = <0xe10a0000 0x28>; interrupts = <0 33 IRQ_TYPE_EDGE_RISING>; clocks = <&iic1_sclk>; clock-names = "sclk"; status = "disabled"; }; };