Commit cd25dd5b authored Jul 10, 2015 by Deepak S Committed by Daniel Vetter Jul 13, 2015

drm/i915: Update PM interrupts before updating the freq



Currently we update the freq before masking the interrupts, which can
allow new interrupts to occur before the frequency has changed. These
extra interrupts might waste some cpu cycles. This patch corrects
this by masking interrupts prior to updating the frequency.

Note from Chris:
"Well it won't waste CPU cycles as the interrupt is also masked by the
threshold limits, but there should be no harm at all in reordering the
patch so, and it does make a certain amount of sense."

Signed-off-by: Deepak S <deepak.s@intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Add note from Chris.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent feecb691

drivers/gpu/drm/i915/intel_pm.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -4482,14 +4482,14 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val)
		"Odd GPU freq value\n"))
		val &= ~1;

		I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));

		if (val != dev_priv->rps.cur_freq) {
		vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
		if (!IS_CHERRYVIEW(dev_priv))
		gen6_set_rps_thresholds(dev_priv, val);
		}

		I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));

		dev_priv->rps.cur_freq = val;
		trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
		}