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Commit ccdbb20a authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: add read/write function for GC CAC programming 



Create a GC_CAC_IND_INDEX/DATA pair of funcitons to program
all the CAC registers

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5e037834

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+6 −0
Original line number Diff line number Diff line
@@ -2018,6 +2018,10 @@ struct amdgpu_device { 
	spinlock_t didt_idx_lock;

	amdgpu_rreg_t			didt_rreg;

	amdgpu_wreg_t			didt_wreg;

	/* protects concurrent gc_cac register access */

	spinlock_t gc_cac_idx_lock;

	amdgpu_rreg_t			gc_cac_rreg;

	amdgpu_wreg_t			gc_cac_wreg;

	/* protects concurrent ENDPOINT (audio) register access */

	spinlock_t audio_endpt_idx_lock;

	amdgpu_block_rreg_t		audio_endpt_rreg;
@@ -2147,6 +2151,8 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 
#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))

#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))

#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))

#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))

#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))

#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))

#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))

#define WREG32_P(reg, val, mask)				\

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

+4 −0
Original line number Diff line number Diff line
@@ -312,6 +312,8 @@ static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device, 
		return RREG32_UVD_CTX(index);

	case CGS_IND_REG__DIDT:

		return RREG32_DIDT(index);

	case CGS_IND_REG_GC_CAC:

		return RREG32_GC_CAC(index);

	case CGS_IND_REG__AUDIO_ENDPT:

		DRM_ERROR("audio endpt register access not implemented.\n");

		return 0;
@@ -336,6 +338,8 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device, 
		return WREG32_UVD_CTX(index, value);

	case CGS_IND_REG__DIDT:

		return WREG32_DIDT(index, value);

	case CGS_IND_REG_GC_CAC:

		return WREG32_GC_CAC(index, value);

	case CGS_IND_REG__AUDIO_ENDPT:

		DRM_ERROR("audio endpt register access not implemented.\n");

		return;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+4 −0
Original line number Diff line number Diff line
@@ -1488,9 +1488,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;

	adev->didt_rreg = &amdgpu_invalid_rreg;

	adev->didt_wreg = &amdgpu_invalid_wreg;

	adev->gc_cac_rreg = &amdgpu_invalid_rreg;

	adev->gc_cac_wreg = &amdgpu_invalid_wreg;

	adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;

	adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;





	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",

		 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,

		 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
@@ -1515,6 +1518,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	spin_lock_init(&adev->pcie_idx_lock);

	spin_lock_init(&adev->uvd_ctx_idx_lock);

	spin_lock_init(&adev->didt_idx_lock);

	spin_lock_init(&adev->gc_cac_idx_lock);

	spin_lock_init(&adev->audio_endpt_idx_lock);



	adev->rmmio_base = pci_resource_start(adev->pdev, 5);

drivers/gpu/drm/amd/amdgpu/vi.c

+25 −0
Original line number Diff line number Diff line
@@ -203,6 +203,29 @@ static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 
	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);

}



static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)

{

	unsigned long flags;

	u32 r;



	spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);

	WREG32(mmGC_CAC_IND_INDEX, (reg));

	r = RREG32(mmGC_CAC_IND_DATA);

	spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);

	return r;

}



static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

{

	unsigned long flags;



	spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);

	WREG32(mmGC_CAC_IND_INDEX, (reg));

	WREG32(mmGC_CAC_IND_DATA, (v));

	spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);

}





static const u32 tonga_mgcg_cgcg_init[] =

{

	mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
@@ -1158,6 +1181,8 @@ static int vi_common_early_init(void *handle) 
	adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;

	adev->didt_rreg = &vi_didt_rreg;

	adev->didt_wreg = &vi_didt_wreg;

	adev->gc_cac_rreg = &vi_gc_cac_rreg;

	adev->gc_cac_wreg = &vi_gc_cac_wreg;



	adev->asic_funcs = &vi_asic_funcs;

drivers/gpu/drm/amd/include/cgs_common.h

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ enum cgs_ind_reg { 
	CGS_IND_REG__SMC,

	CGS_IND_REG__UVD_CTX,

	CGS_IND_REG__DIDT,

	CGS_IND_REG_GC_CAC,

	CGS_IND_REG__AUDIO_ENDPT

};