Commit ccb8b12c authored May 22, 2014 by Stéphane Marchesin Committed by Thierry Reding Jun 09, 2014

drm/tegra: sor - Remove pixel clock rounding



The code currently rounds up the clock to the next MHZ, which is
rounding up a 69.5MHz clock to 70MHz on my machine. This in turn
prevents the display from syncing. Removing this rounding fixes eDP
for me.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

parent 1b0c7b48

drivers/gpu/drm/tegra/sor.c

+0 −3

Original line number	Diff line number	Diff line
		@@ -876,9 +876,6 @@ static int tegra_output_sor_setup_clock(struct tegra_output *output,
		struct tegra_sor *sor = to_sor(output);
		int err;

		/* round to next MHz */
		pclk = DIV_ROUND_UP(pclk, 1000000) * 1000000;

		err = clk_set_parent(clk, sor->clk_parent);
		if (err < 0) {
		dev_err(sor->dev, "failed to set parent clock: %d\n", err);