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Commit cb9456b5 authored by Iain Paton's avatar Iain Paton Committed by Shawn Guo
Browse files

ARM: dts: imx6: RIoTboard explicitly define pad settings 



Instead of relying on defaults or bootloader settings, explicitly define
all pad settings.

This resolves reported issues of no analogue audio output.

Signed-off-by: default avatarIain Paton <ipaton0@gmail.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent e7779620

arch/arm/boot/dts/imx6dl-riotboard.dts

+16 −16
Original line number Diff line number Diff line
@@ -334,10 +334,10 @@ 
	imx6-riotboard {

		pinctrl_audmux: audmuxgrp {

			fsl,pins = <

				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x8000000

				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x8000000

				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x8000000

				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x8000000

				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0

				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0

				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0

				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0

				MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0		/* CAM_MCLK */

			>;

		};
@@ -375,7 +375,7 @@ 
			fsl,pins = <

				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0

				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x80000000

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
@@ -388,9 +388,9 @@ 
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0		/* AR8035 pin strapping: MODE#1: pull up */

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0		/* AR8035 pin strapping: MODE#3: pull up */

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x130b0		/* AR8035 pin strapping: MODE#0: pull down */

				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0xc0000000	/* GPIO16 -> AR8035 25MHz */

				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8	/* GPIO16 -> AR8035 25MHz */

			        MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x130b0		/* RGMII_nRST */

				MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x80000000	/* AR8035 interrupt */

				MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x180b0		/* AR8035 interrupt */

				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1

			>;

		};
@@ -425,8 +425,8 @@ 


		pinctrl_led: ledgrp {

			fsl,pins = <

				MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x80000000	/* user led0 */

				MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x80000000	/* user led1 */

				MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1b0b1	/* user led0 */

				MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x1b0b1	/* user led1 */

			>;

		};
@@ -492,8 +492,8 @@ 
		pinctrl_usbotg: usbotggrp {

			fsl,pins = <

				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059

				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x80000000	/* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */

				MX6QDL_PAD_EIM_D21__USB_OTG_OC		0x80000000

				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x000b0	/* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */

				MX6QDL_PAD_EIM_D21__USB_OTG_OC		0x1b0b0

			>;

		};
@@ -505,8 +505,8 @@ 
				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059

				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059

				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059

				MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x80000000	/* SD2 CD */

				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x80000000	/* SD2 WP */

				MX6QDL_PAD_GPIO_4__GPIO1_IO04		0x1b0b0	/* SD2 CD */

				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1f0b0	/* SD2 WP */

			>;

		};
@@ -518,8 +518,8 @@ 
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059

				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059

				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059

				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x80000000	/* SD3 CD */

				MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x80000000	/* SD3 WP */

				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x1b0b0	/* SD3 CD */

				MX6QDL_PAD_SD3_DAT4__GPIO7_IO01		0x1f0b0	/* SD3 WP */

			>;

		};
@@ -531,7 +531,7 @@ 
				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059

				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059

				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059

				MX6QDL_PAD_NANDF_ALE__GPIO6_IO08	0x80000000	/* SD4 RST (eMMC) */

				MX6QDL_PAD_NANDF_ALE__GPIO6_IO08	0x17059	/* SD4 RST (eMMC) */

			>;

		};

	};