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Commit cb5571fc authored by Yakir Yang's avatar Yakir Yang
Browse files

drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 



There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit bcec20fd ("drm: bridge: analogix/dp: add some rk3288 special
registers setting").

The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.

Signed-off-by: default avatarYakir Yang <ykk@rock-chips.com>
Reviewed-by: default avatarSean Paul <seanpaul@chromium.org>
Reviewed-by: default avatarTomasz Figa <tomasz.figa@chromium.com>
Tested-by: default avatarJavier Martinez Canillas <javier@osg.samsung.com>
parent d9c900b0

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h

+2 −2
Original line number Diff line number Diff line
@@ -163,8 +163,8 @@ 
#define HSYNC_POLARITY_CFG			(0x1 << 0)



/* ANALOGIX_DP_PLL_REG_1 */

#define REF_CLK_24M				(0x1 << 1)

#define REF_CLK_27M				(0x0 << 1)

#define REF_CLK_24M				(0x1 << 0)

#define REF_CLK_27M				(0x0 << 0)



/* ANALOGIX_DP_LANE_MAP */

#define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)