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Commit cb2d47a4 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-amdkfd-next-2015-06-03' of git://people.freedesktop.org/~gabbayo/linux into drm-next 

drm-amdkfd-next-2015-06-03:

- Add the H/W debugger support module, including new IOCTLs to:
  - register/unregister a process as a debugged process
  - Set address watch-point in the debugged process's GPU kernel
  - Do a wave control operation in the debugged process's waves
  See the commit messages for more details on the available operations.

  The debugged process can only perform debug operation on itself. It is
  blocked by the amdkfd+H/W from performing operations on other processes's
  waves or GPU kernels. The blocking is done by setting the VMID and PASID of
  the debugged process in the packets that are sent to the CP with the debug
  instructions.

- Add support for static user-mode queues. These queues are regular queues,
  but because they belong to the debugged process, we need to make sure the CP
  doesn't preempt them during a debug operation. Therefore, we mark them as
  static for the CP ignore them during preemption.

- Support killing all the waves when a process is terminated. This is needed
  in case a process is terminated but we can't UNMAP its queues (can occur due
  to several reasons). In that case, the CP could be stuck unless we kill all
  its waves. This function is *very* important as it provides the kernel a high
  level of control over the GPU. The reason we didn't upstream this function
  so far, is because it is implemented using the H/W debugger module functions,
  so we had to wait until we can upstream the H/W debugger module.

- Replace declaration of bitmap from unsigned long to standard DECLARE_BITMAP

* tag 'drm-amdkfd-next-2015-06-03' of git://people.freedesktop.org/~gabbayo/linux:
  drm/amdkfd: Enforce kill all waves on process termination
  drm/radeon: Add ATC VMID<-->PASID functions to kfd->kgd
  drm/amdkfd: Implement address watch debugger IOCTL
  drm/amdkfd: Implement wave control debugger IOCTL
  drm/amdkfd: Implement (un)register debugger IOCTLs
  drm/amdkfd: Add address watch operation to debugger
  drm/amdkfd: Add wave control operation to debugger
  drm/amdkfd: Add skeleton H/W debugger module support
  drm/amdkfd: Add static user-mode queues support
  drm/amdkfd: add H/W debugger IOCTL set definitions
  drm/radeon: Add H/W debugger kfd->kgd functions
  drm/amdkfd: Use DECLARE_BITMAP
parents 3e8d222f c3447e81

drivers/gpu/drm/amd/amdkfd/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \ 
		kfd_kernel_queue_vi.o kfd_packet_manager.o \

		kfd_process_queue_manager.o kfd_device_queue_manager.o \

		kfd_device_queue_manager_cik.o kfd_device_queue_manager_vi.o \

		kfd_interrupt.o kfd_events.o cik_event_interrupt.o

		kfd_interrupt.o kfd_events.o cik_event_interrupt.o \

		kfd_dbgdev.o kfd_dbgmgr.o



obj-$(CONFIG_HSA_AMD)	+= amdkfd.o

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

+308 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
#include <asm/processor.h>

#include "kfd_priv.h"

#include "kfd_device_queue_manager.h"

#include "kfd_dbgmgr.h"



static long kfd_ioctl(struct file *, unsigned int, unsigned long);

static int kfd_open(struct inode *, struct file *);
@@ -432,6 +433,301 @@ static int kfd_ioctl_set_memory_policy(struct file *filep, 
	return err;

}



static int kfd_ioctl_dbg_register(struct file *filep,

				struct kfd_process *p, void *data)

{

	struct kfd_ioctl_dbg_register_args *args = data;

	struct kfd_dev *dev;

	struct kfd_dbgmgr *dbgmgr_ptr;

	struct kfd_process_device *pdd;

	bool create_ok;

	long status = 0;



	dev = kfd_device_by_id(args->gpu_id);

	if (dev == NULL)

		return -EINVAL;



	if (dev->device_info->asic_family == CHIP_CARRIZO) {

		pr_debug("kfd_ioctl_dbg_register not supported on CZ\n");

		return -EINVAL;

	}



	mutex_lock(kfd_get_dbgmgr_mutex());

	mutex_lock(&p->mutex);



	/*

	 * make sure that we have pdd, if this the first queue created for

	 * this process

	 */

	pdd = kfd_bind_process_to_device(dev, p);

	if (IS_ERR(pdd)) {

		mutex_unlock(&p->mutex);

		mutex_unlock(kfd_get_dbgmgr_mutex());

		return PTR_ERR(pdd);

	}



	if (dev->dbgmgr == NULL) {

		/* In case of a legal call, we have no dbgmgr yet */

		create_ok = kfd_dbgmgr_create(&dbgmgr_ptr, dev);

		if (create_ok) {

			status = kfd_dbgmgr_register(dbgmgr_ptr, p);

			if (status != 0)

				kfd_dbgmgr_destroy(dbgmgr_ptr);

			else

				dev->dbgmgr = dbgmgr_ptr;

		}

	} else {

		pr_debug("debugger already registered\n");

		status = -EINVAL;

	}



	mutex_unlock(&p->mutex);

	mutex_unlock(kfd_get_dbgmgr_mutex());



	return status;

}



static int kfd_ioctl_dbg_unrgesiter(struct file *filep,

				struct kfd_process *p, void *data)

{

	struct kfd_ioctl_dbg_unregister_args *args = data;

	struct kfd_dev *dev;

	long status;



	dev = kfd_device_by_id(args->gpu_id);

	if (dev == NULL)

		return -EINVAL;



	if (dev->device_info->asic_family == CHIP_CARRIZO) {

		pr_debug("kfd_ioctl_dbg_unrgesiter not supported on CZ\n");

		return -EINVAL;

	}



	mutex_lock(kfd_get_dbgmgr_mutex());



	status = kfd_dbgmgr_unregister(dev->dbgmgr, p);

	if (status == 0) {

		kfd_dbgmgr_destroy(dev->dbgmgr);

		dev->dbgmgr = NULL;

	}



	mutex_unlock(kfd_get_dbgmgr_mutex());



	return status;

}



/*

 * Parse and generate variable size data structure for address watch.

 * Total size of the buffer and # watch points is limited in order

 * to prevent kernel abuse. (no bearing to the much smaller HW limitation

 * which is enforced by dbgdev module)

 * please also note that the watch address itself are not "copied from user",

 * since it be set into the HW in user mode values.

 *

 */

static int kfd_ioctl_dbg_address_watch(struct file *filep,

					struct kfd_process *p, void *data)

{

	struct kfd_ioctl_dbg_address_watch_args *args = data;

	struct kfd_dev *dev;

	struct dbg_address_watch_info aw_info;

	unsigned char *args_buff;

	long status;

	void __user *cmd_from_user;

	uint64_t watch_mask_value = 0;

	unsigned int args_idx = 0;



	memset((void *) &aw_info, 0, sizeof(struct dbg_address_watch_info));



	dev = kfd_device_by_id(args->gpu_id);

	if (dev == NULL)

		return -EINVAL;



	if (dev->device_info->asic_family == CHIP_CARRIZO) {

		pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");

		return -EINVAL;

	}



	cmd_from_user = (void __user *) args->content_ptr;



	/* Validate arguments */



	if ((args->buf_size_in_bytes > MAX_ALLOWED_AW_BUFF_SIZE) ||

		(args->buf_size_in_bytes <= sizeof(*args)) ||

		(cmd_from_user == NULL))

		return -EINVAL;



	/* this is the actual buffer to work with */



	args_buff = kmalloc(args->buf_size_in_bytes -

					sizeof(*args), GFP_KERNEL);

	if (args_buff == NULL)

		return -ENOMEM;



	status = copy_from_user(args_buff, cmd_from_user,

				args->buf_size_in_bytes - sizeof(*args));



	if (status != 0) {

		pr_debug("Failed to copy address watch user data\n");

		kfree(args_buff);

		return -EINVAL;

	}



	aw_info.process = p;



	aw_info.num_watch_points = *((uint32_t *)(&args_buff[args_idx]));

	args_idx += sizeof(aw_info.num_watch_points);



	aw_info.watch_mode = (enum HSA_DBG_WATCH_MODE *) &args_buff[args_idx];

	args_idx += sizeof(enum HSA_DBG_WATCH_MODE) * aw_info.num_watch_points;



	/*

	 * set watch address base pointer to point on the array base

	 * within args_buff

	 */

	aw_info.watch_address = (uint64_t *) &args_buff[args_idx];



	/* skip over the addresses buffer */

	args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points;



	if (args_idx >= args->buf_size_in_bytes) {

		kfree(args_buff);

		return -EINVAL;

	}



	watch_mask_value = (uint64_t) args_buff[args_idx];



	if (watch_mask_value > 0) {

		/*

		 * There is an array of masks.

		 * set watch mask base pointer to point on the array base

		 * within args_buff

		 */

		aw_info.watch_mask = (uint64_t *) &args_buff[args_idx];



		/* skip over the masks buffer */

		args_idx += sizeof(aw_info.watch_mask) *

				aw_info.num_watch_points;

	} else {

		/* just the NULL mask, set to NULL and skip over it */

		aw_info.watch_mask = NULL;

		args_idx += sizeof(aw_info.watch_mask);

	}



	if (args_idx > args->buf_size_in_bytes) {

		kfree(args_buff);

		return -EINVAL;

	}



	/* Currently HSA Event is not supported for DBG */

	aw_info.watch_event = NULL;



	mutex_lock(kfd_get_dbgmgr_mutex());



	status = kfd_dbgmgr_address_watch(dev->dbgmgr, &aw_info);



	mutex_unlock(kfd_get_dbgmgr_mutex());



	kfree(args_buff);



	return status;

}



/* Parse and generate fixed size data structure for wave control */

static int kfd_ioctl_dbg_wave_control(struct file *filep,

					struct kfd_process *p, void *data)

{

	struct kfd_ioctl_dbg_wave_control_args *args = data;

	struct kfd_dev *dev;

	struct dbg_wave_control_info wac_info;

	unsigned char *args_buff;

	uint32_t computed_buff_size;

	long status;

	void __user *cmd_from_user;

	unsigned int args_idx = 0;



	memset((void *) &wac_info, 0, sizeof(struct dbg_wave_control_info));



	/* we use compact form, independent of the packing attribute value */

	computed_buff_size = sizeof(*args) +

				sizeof(wac_info.mode) +

				sizeof(wac_info.operand) +

				sizeof(wac_info.dbgWave_msg.DbgWaveMsg) +

				sizeof(wac_info.dbgWave_msg.MemoryVA) +

				sizeof(wac_info.trapId);



	dev = kfd_device_by_id(args->gpu_id);

	if (dev == NULL)

		return -EINVAL;



	if (dev->device_info->asic_family == CHIP_CARRIZO) {

		pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");

		return -EINVAL;

	}



	/* input size must match the computed "compact" size */

	if (args->buf_size_in_bytes != computed_buff_size) {

		pr_debug("size mismatch, computed : actual %u : %u\n",

				args->buf_size_in_bytes, computed_buff_size);

		return -EINVAL;

	}



	cmd_from_user = (void __user *) args->content_ptr;



	if (cmd_from_user == NULL)

		return -EINVAL;



	/* this is the actual buffer to work with */



	args_buff = kmalloc(args->buf_size_in_bytes - sizeof(*args),

			GFP_KERNEL);



	if (args_buff == NULL)

		return -ENOMEM;



	/* Now copy the entire buffer from user */

	status = copy_from_user(args_buff, cmd_from_user,

				args->buf_size_in_bytes - sizeof(*args));

	if (status != 0) {

		pr_debug("Failed to copy wave control user data\n");

		kfree(args_buff);

		return -EINVAL;

	}



	/* move ptr to the start of the "pay-load" area */

	wac_info.process = p;



	wac_info.operand = *((enum HSA_DBG_WAVEOP *)(&args_buff[args_idx]));

	args_idx += sizeof(wac_info.operand);



	wac_info.mode = *((enum HSA_DBG_WAVEMODE *)(&args_buff[args_idx]));

	args_idx += sizeof(wac_info.mode);



	wac_info.trapId = *((uint32_t *)(&args_buff[args_idx]));

	args_idx += sizeof(wac_info.trapId);



	wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value =

					*((uint32_t *)(&args_buff[args_idx]));

	wac_info.dbgWave_msg.MemoryVA = NULL;



	mutex_lock(kfd_get_dbgmgr_mutex());



	pr_debug("Calling dbg manager process %p, operand %u, mode %u, trapId %u, message %u\n",

			wac_info.process, wac_info.operand,

			wac_info.mode, wac_info.trapId,

			wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);



	status = kfd_dbgmgr_wave_control(dev->dbgmgr, &wac_info);



	pr_debug("Returned status of dbg manager is %ld\n", status);



	mutex_unlock(kfd_get_dbgmgr_mutex());



	kfree(args_buff);



	return status;

}



static int kfd_ioctl_get_clock_counters(struct file *filep,

				struct kfd_process *p, void *data)

{
@@ -612,6 +908,18 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { 


	AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,

			kfd_ioctl_wait_events, 0),



	AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER,

			kfd_ioctl_dbg_register, 0),



	AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER,

			kfd_ioctl_dbg_unrgesiter, 0),



	AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH,

			kfd_ioctl_dbg_address_watch, 0),



	AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL,

			kfd_ioctl_dbg_wave_control, 0),

};



#define AMDKFD_CORE_IOCTL_COUNT	ARRAY_SIZE(amdkfd_ioctls)

drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c

0 → 100644
+886 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h

0 → 100644
+193 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2014 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 */



#ifndef KFD_DBGDEV_H_

#define KFD_DBGDEV_H_



enum {

	SQ_CMD_VMID_OFFSET = 28,

	ADDRESS_WATCH_CNTL_OFFSET = 24

};



enum {

	PRIV_QUEUE_SYNC_TIME_MS = 200

};



/* CONTEXT reg space definition */

enum {

	CONTEXT_REG_BASE = 0xA000,

	CONTEXT_REG_END = 0xA400,

	CONTEXT_REG_SIZE = CONTEXT_REG_END - CONTEXT_REG_BASE

};



/* USER CONFIG reg space definition */

enum {

	USERCONFIG_REG_BASE = 0xC000,

	USERCONFIG_REG_END = 0x10000,

	USERCONFIG_REG_SIZE = USERCONFIG_REG_END - USERCONFIG_REG_BASE

};



/* CONFIG reg space definition */

enum {

	CONFIG_REG_BASE = 0x2000,	/* in dwords */

	CONFIG_REG_END = 0x2B00,

	CONFIG_REG_SIZE = CONFIG_REG_END - CONFIG_REG_BASE

};



/* SH reg space definition */

enum {

	SH_REG_BASE = 0x2C00,

	SH_REG_END = 0x3000,

	SH_REG_SIZE = SH_REG_END - SH_REG_BASE

};



enum SQ_IND_CMD_CMD {

	SQ_IND_CMD_CMD_NULL = 0x00000000,

	SQ_IND_CMD_CMD_HALT = 0x00000001,

	SQ_IND_CMD_CMD_RESUME = 0x00000002,

	SQ_IND_CMD_CMD_KILL = 0x00000003,

	SQ_IND_CMD_CMD_DEBUG = 0x00000004,

	SQ_IND_CMD_CMD_TRAP = 0x00000005,

};



enum SQ_IND_CMD_MODE {

	SQ_IND_CMD_MODE_SINGLE = 0x00000000,

	SQ_IND_CMD_MODE_BROADCAST = 0x00000001,

	SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002,

	SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003,

	SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004,

};



union SQ_IND_INDEX_BITS {

	struct {

		uint32_t wave_id:4;

		uint32_t simd_id:2;

		uint32_t thread_id:6;

		 uint32_t:1;

		uint32_t force_read:1;

		uint32_t read_timeout:1;

		uint32_t unindexed:1;

		uint32_t index:16;



	} bitfields, bits;

	uint32_t u32All;

	signed int i32All;

	float f32All;

};



union SQ_IND_CMD_BITS {

	struct {

		uint32_t data:32;

	} bitfields, bits;

	uint32_t u32All;

	signed int i32All;

	float f32All;

};



union SQ_CMD_BITS {

	struct {

		uint32_t cmd:3;

		 uint32_t:1;

		uint32_t mode:3;

		uint32_t check_vmid:1;

		uint32_t trap_id:3;

		 uint32_t:5;

		uint32_t wave_id:4;

		uint32_t simd_id:2;

		 uint32_t:2;

		uint32_t queue_id:3;

		 uint32_t:1;

		uint32_t vm_id:4;

	} bitfields, bits;

	uint32_t u32All;

	signed int i32All;

	float f32All;

};



union SQ_IND_DATA_BITS {

	struct {

		uint32_t data:32;

	} bitfields, bits;

	uint32_t u32All;

	signed int i32All;

	float f32All;

};



union GRBM_GFX_INDEX_BITS {

	struct {

		uint32_t instance_index:8;

		uint32_t sh_index:8;

		uint32_t se_index:8;

		 uint32_t:5;

		uint32_t sh_broadcast_writes:1;

		uint32_t instance_broadcast_writes:1;

		uint32_t se_broadcast_writes:1;

	} bitfields, bits;

	uint32_t u32All;

	signed int i32All;

	float f32All;

};



union TCP_WATCH_ADDR_H_BITS {

	struct {

		uint32_t addr:16;

		 uint32_t:16;



	} bitfields, bits;

	uint32_t u32All;

	signed int i32All;

	float f32All;

};



union TCP_WATCH_ADDR_L_BITS {

	struct {

		uint32_t:6;

		uint32_t addr:26;

	} bitfields, bits;

	uint32_t u32All;

	signed int i32All;

	float f32All;

};



enum {

	QUEUESTATE__INVALID = 0, /* so by default we'll get invalid state */

	QUEUESTATE__ACTIVE_COMPLETION_PENDING,

	QUEUESTATE__ACTIVE

};



union ULARGE_INTEGER {

	struct {

		uint32_t low_part;

		uint32_t high_part;

	} u;

	unsigned long long quad_part;

};





#define KFD_CIK_VMID_START_OFFSET (8)

#define KFD_CIK_VMID_END_OFFSET (KFD_CIK_VMID_START_OFFSET + (8))





void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,

			enum DBGDEV_TYPE type);



#endif	/* KFD_DBGDEV_H_ */

drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c

0 → 100644
+168 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2014 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#include <linux/types.h>

#include <linux/kernel.h>

#include <linux/log2.h>

#include <linux/sched.h>

#include <linux/slab.h>

#include <linux/device.h>



#include "kfd_priv.h"

#include "cik_regs.h"

#include "kfd_pm4_headers.h"

#include "kfd_pm4_headers_diq.h"

#include "kfd_dbgmgr.h"

#include "kfd_dbgdev.h"



static DEFINE_MUTEX(kfd_dbgmgr_mutex);



struct mutex *kfd_get_dbgmgr_mutex(void)

{

	return &kfd_dbgmgr_mutex;

}





static void kfd_dbgmgr_uninitialize(struct kfd_dbgmgr *pmgr)

{

	BUG_ON(!pmgr);



	kfree(pmgr->dbgdev);



	pmgr->dbgdev = NULL;

	pmgr->pasid = 0;

	pmgr->dev = NULL;

}



void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr)

{

	if (pmgr != NULL) {

		kfd_dbgmgr_uninitialize(pmgr);

		kfree(pmgr);

	}

}



bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev)

{

	enum DBGDEV_TYPE type = DBGDEV_TYPE_DIQ;

	struct kfd_dbgmgr *new_buff;



	BUG_ON(pdev == NULL);

	BUG_ON(!pdev->init_complete);



	new_buff = kfd_alloc_struct(new_buff);

	if (!new_buff) {

		pr_err("amdkfd: Failed to allocate dbgmgr instance\n");

		return false;

	}



	new_buff->pasid = 0;

	new_buff->dev = pdev;

	new_buff->dbgdev = kfd_alloc_struct(new_buff->dbgdev);

	if (!new_buff->dbgdev) {

		pr_err("amdkfd: Failed to allocate dbgdev instance\n");

		kfree(new_buff);

		return false;

	}



	/* get actual type of DBGDevice cpsch or not */

	if (sched_policy == KFD_SCHED_POLICY_NO_HWS)

		type = DBGDEV_TYPE_NODIQ;



	kfd_dbgdev_init(new_buff->dbgdev, pdev, type);

	*ppmgr = new_buff;



	return true;

}



long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p)

{

	BUG_ON(!p || !pmgr || !pmgr->dbgdev);



	if (pmgr->pasid != 0) {

		pr_debug("H/W debugger is already active using pasid %d\n",

				pmgr->pasid);

		return -EBUSY;

	}



	/* remember pasid */

	pmgr->pasid = p->pasid;



	/* provide the pqm for diq generation */

	pmgr->dbgdev->pqm = &p->pqm;



	/* activate the actual registering */

	pmgr->dbgdev->dbgdev_register(pmgr->dbgdev);



	return 0;

}



long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p)

{

	BUG_ON(!p || !pmgr || !pmgr->dbgdev);



	/* Is the requests coming from the already registered process? */

	if (pmgr->pasid != p->pasid) {

		pr_debug("H/W debugger is not registered by calling pasid %d\n",

				p->pasid);

		return -EINVAL;

	}



	pmgr->dbgdev->dbgdev_unregister(pmgr->dbgdev);



	pmgr->pasid = 0;



	return 0;

}



long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr,

				struct dbg_wave_control_info *wac_info)

{

	BUG_ON(!pmgr || !pmgr->dbgdev || !wac_info);



	/* Is the requests coming from the already registered process? */

	if (pmgr->pasid != wac_info->process->pasid) {

		pr_debug("H/W debugger support was not registered for requester pasid %d\n",

				wac_info->process->pasid);

		return -EINVAL;

	}



	return (long) pmgr->dbgdev->dbgdev_wave_control(pmgr->dbgdev, wac_info);

}



long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr,

				struct dbg_address_watch_info *adw_info)

{

	BUG_ON(!pmgr || !pmgr->dbgdev || !adw_info);





	/* Is the requests coming from the already registered process? */

	if (pmgr->pasid != adw_info->process->pasid) {

		pr_debug("H/W debugger support was not registered for requester pasid %d\n",

				adw_info->process->pasid);

		return -EINVAL;

	}



	return (long) pmgr->dbgdev->dbgdev_address_watch(pmgr->dbgdev,

							adw_info);

}