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Commit c9a803fb authored by LEROY Christophe's avatar LEROY Christophe Committed by Scott Wood
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powerpc/8xx: _PMD_PRESENT already set in level 1 entries 



When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent 4094f28f

arch/powerpc/kernel/head_8xx.S

+0 −2
Original line number Diff line number Diff line
@@ -342,7 +342,6 @@ InstructionTLBMiss: 
	/* We have a pte table, so load the MI_TWC with the attributes

	 * for this "segment."

	 */

	ori	r11,r11,1		/* Set valid bit */

	MTSPR_CPU6(SPRN_MI_TWC, r11, r3)	/* Set segment attributes */

	mfspr	r11, SPRN_SRR0	/* Get effective address of fault */

	/* Extract level 2 index */
@@ -419,7 +418,6 @@ DataStoreTLBMiss: 
	rlwimi	r10, r11, 0, 0, 32 - PAGE_SHIFT - 1	/* Add level 2 base */

	lwz	r10, 0(r10)	/* Get the pte */



	ori	r11, r11, 1	/* Set valid bit in physical L2 page */

	/* Insert the Guarded flag into the TWC from the Linux PTE.

	 * It is bit 27 of both the Linux PTE and the TWC (at least

	 * I got that right :-).  It will be better when we can put