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Commit c9468682 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k: Fix antenna diversity init for AR9565 



Program the HW registers (AR_PHY_CCK_DETECT, AR_PHY_MC_GAIN_CTRL)
with the correct values for AR9565 to allow LNA combining.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 7e12d6a4

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

+16 −1
Original line number Diff line number Diff line
@@ -3659,9 +3659,23 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 
		if (AR_SREV_9565(ah)) {

			if (common->bt_ant_diversity) {

				regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S);



				REG_SET_BIT(ah, AR_PHY_RESTART,

					    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);



				/* Force WLAN LNA diversity ON */

				REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,

					    AR_BTCOEX_WL_LNADIV_FORCE_ON);

			} else {

				regval &= ~(1 << AR_PHY_ANT_DIV_LNADIV_S);

				regval &= ~(1 << AR_PHY_ANT_SW_RX_PROT_S);



				REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,

					    (1 << AR_PHY_ANT_SW_RX_PROT_S));



				/* Force WLAN LNA diversity OFF */

				REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,

					    AR_BTCOEX_WL_LNADIV_FORCE_ON);

			}

		}
@@ -3672,7 +3686,8 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 
		regval &= (~AR_FAST_DIV_ENABLE);

		regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;



		if (AR_SREV_9485(ah) && common->bt_ant_diversity)

		if ((AR_SREV_9485(ah) || AR_SREV_9565(ah))

		    && common->bt_ant_diversity)

			regval |= AR_FAST_DIV_ENABLE;



		REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

+12 −5
Original line number Diff line number Diff line
@@ -1488,18 +1488,25 @@ static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) 
		}

	} else if (AR_SREV_9565(ah)) {

		if (enable) {

			REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,

				    AR_ANT_DIV_ENABLE);

			REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,

				    (1 << AR_PHY_ANT_SW_RX_PROT_S));

			if (ah->curchan && IS_CHAN_2GHZ(ah->curchan))

			REG_SET_BIT(ah, AR_PHY_CCK_DETECT,

				    AR_FAST_DIV_ENABLE);

			REG_SET_BIT(ah, AR_PHY_RESTART,

				    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);

			REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,

				    AR_BTCOEX_WL_LNADIV_FORCE_ON);

		} else {

			REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);

			REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,

				    AR_ANT_DIV_ENABLE);

			REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,

				    (1 << AR_PHY_ANT_SW_RX_PROT_S));

			REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);

			REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,

				    AR_FAST_DIV_ENABLE);

			REG_CLR_BIT(ah, AR_PHY_RESTART,

				    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);

			REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,

				    AR_BTCOEX_WL_LNADIV_FORCE_ON);