Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c9224faa authored by Brad Volkin's avatar Brad Volkin Committed by Daniel Vetter
Browse files

drm/i915: Add some L3 registers to the parser whitelist 



Beignet needs these in order to program the L3 cache config for
OpenCL workloads, particularly when using SLM.

Signed-off-by: default avatarBrad Volkin <bradley.d.volkin@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent beff0d0f

drivers/gpu/drm/i915/i915_cmd_parser.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -426,6 +426,9 @@ static const u32 gen7_render_regs[] = { 
	GEN7_SO_WRITE_OFFSET(1),

	GEN7_SO_WRITE_OFFSET(1),

	GEN7_SO_WRITE_OFFSET(2),

	GEN7_SO_WRITE_OFFSET(2),

	GEN7_SO_WRITE_OFFSET(3),

	GEN7_SO_WRITE_OFFSET(3),

	GEN7_L3SQCREG1,

	GEN7_L3CNTLREG2,

	GEN7_L3CNTLREG3,

};

};





static const u32 gen7_blt_regs[] = {

static const u32 gen7_blt_regs[] = {

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -4670,6 +4670,8 @@ enum punit_power_well { 
#define GEN7_L3CNTLREG1				0xB01C

#define GEN7_L3CNTLREG1				0xB01C

#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C

#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C

#define  GEN7_L3AGDIS				(1<<19)

#define  GEN7_L3AGDIS				(1<<19)

#define GEN7_L3CNTLREG2				0xB020

#define GEN7_L3CNTLREG3				0xB024





#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030

#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030

#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000

#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000