Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c83155a6 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
Browse files

drm/i915/skl: Move gen9 pm initialization into its own branch 



Gen9 is different enough (for instance, fetching the memory latency
values is different from ILK+) to not take the HAS_PCH_SPLIT() branch,
so let's prefer a clean separation.

v2: Rebase on top of the broadwell_init_clock_gating() name change

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 6af31a65

drivers/gpu/drm/i915/intel_pm.c

+3 −3
Original line number Diff line number Diff line
@@ -7397,7 +7397,9 @@ void intel_init_pm(struct drm_device *dev) 
		i915_ironlake_get_mem_freq(dev);



	/* For FIFO watermark updates */

	if (HAS_PCH_SPLIT(dev)) {

	if (IS_GEN9(dev)) {

		dev_priv->display.init_clock_gating = gen9_init_clock_gating;

	} else if (HAS_PCH_SPLIT(dev)) {

		ilk_setup_wm_latency(dev);



		if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
@@ -7421,8 +7423,6 @@ void intel_init_pm(struct drm_device *dev) 
			dev_priv->display.init_clock_gating = haswell_init_clock_gating;

		else if (INTEL_INFO(dev)->gen == 8)

			dev_priv->display.init_clock_gating = broadwell_init_clock_gating;

		else if (INTEL_INFO(dev)->gen == 9)

			dev_priv->display.init_clock_gating = gen9_init_clock_gating;

	} else if (IS_CHERRYVIEW(dev)) {

		dev_priv->display.update_wm = cherryview_update_wm;

		dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;