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Commit c706c7eb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm 

Pull ARM development updates from Russell King:
 "Included in this update:

   - moving PSCI code from ARM64/ARM to drivers/

   - removal of some architecture internals from global kernel view

   - addition of software based "privileged no access" support using the
     old domains register to turn off the ability for kernel
     loads/stores to access userspace.  Only the proper accessors will
     be usable.

   - addition of early fixup support for early console

   - re-addition (and reimplementation) of OMAP special interconnect
     barrier

   - removal of finish_arch_switch()

   - only expose cpuX/online in sysfs if hotpluggable

   - a number of code cleanups"

* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (41 commits)
  ARM: software-based priviledged-no-access support
  ARM: entry: provide uaccess assembly macro hooks
  ARM: entry: get rid of multiple macro definitions
  ARM: 8421/1: smp: Collapse arch_cpu_idle_dead() into cpu_die()
  ARM: uaccess: provide uaccess_save_and_enable() and uaccess_restore()
  ARM: mm: improve do_ldrd_abort macro
  ARM: entry: ensure that IRQs are enabled when calling syscall_trace_exit()
  ARM: entry: efficiency cleanups
  ARM: entry: get rid of asm_trace_hardirqs_on_cond
  ARM: uaccess: simplify user access assembly
  ARM: domains: remove DOMAIN_TABLE
  ARM: domains: keep vectors in separate domain
  ARM: domains: get rid of manager mode for user domain
  ARM: domains: move initial domain setting value to asm/domains.h
  ARM: domains: provide domain_mask()
  ARM: domains: switch to keeping domain value in register
  ARM: 8419/1: dma-mapping: harmonize definition of DMA_ERROR_CODE
  ARM: 8417/1: refactor bitops functions with BIT_MASK() and BIT_WORD()
  ARM: 8416/1: Feroceon: use of_iomap() to map register base
  ARM: 8415/1: early fixmap support for earlycon
  ...
parents 79b0691d 3ff32a0d

Documentation/devicetree/bindings/arm/l2cc.txt

+6 −0
Original line number Diff line number Diff line
@@ -67,6 +67,12 @@ Optional properties: 
  disable if zero.

- arm,prefetch-offset : Override prefetch offset value. Valid values are

  0-7, 15, 23, and 31.

- arm,shared-override : The default behavior of the pl310 cache controller with

  respect to the shareable attribute is to transform "normal memory

  non-cacheable transactions" into "cacheable no allocate" (for reads) or

  "write through no write allocate" (for writes).

  On systems where this may cause DMA buffer corruption, this property must be

  specified to indicate that such transforms are precluded.

- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>

  (forcibly enable), property absent (retain settings set by firmware)

- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),

Documentation/devicetree/bindings/arm/pmu.txt

+9 −3
Original line number Diff line number Diff line
@@ -26,13 +26,19 @@ Required properties: 


Optional properties:



- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles

                       to CPU nodes corresponding directly to the affinity of

- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU

                       nodes corresponding directly to the affinity of

		       the SPIs listed in the interrupts property.



                       When using a PPI, specifies a list of phandles to CPU

		       nodes corresponding to the set of CPUs which have

		       a PMU of this type signalling the PPI listed in the

		       interrupts property.



                       This property should be present when there is more than

		       a single SPI.





- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd

                     events.

MAINTAINERS

+13 −2
Original line number Diff line number Diff line
@@ -806,11 +806,13 @@ F: arch/arm/include/asm/floppy.h 
ARM PMU PROFILING AND DEBUGGING

M:	Will Deacon <will.deacon@arm.com>

S:	Maintained

F:	arch/arm/kernel/perf_event*

F:	arch/arm/kernel/perf_*

F:	arch/arm/oprofile/common.c

F:	arch/arm/include/asm/pmu.h

F:	arch/arm/kernel/hw_breakpoint.c

F:	arch/arm/include/asm/hw_breakpoint.h

F:	arch/arm/include/asm/perf_event.h

F:	drivers/perf/arm_pmu.c

F:	include/linux/perf/arm_pmu.h



ARM PORT

M:	Russell King <linux@arm.linux.org.uk>
@@ -8120,6 +8122,15 @@ F: include/linux/power_supply.h 
F:	drivers/power/

X:	drivers/power/avs/



POWER STATE COORDINATION INTERFACE (PSCI)

M:	Mark Rutland <mark.rutland@arm.com>

M:	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

L:	linux-arm-kernel@lists.infradead.org

S:	Maintained

F:	drivers/firmware/psci.c

F:	include/linux/psci.h

F:	include/uapi/linux/psci.h



PNP SUPPORT

M:	"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>

S:	Maintained

arch/arm/Kconfig

+20 −5
Original line number Diff line number Diff line
@@ -188,6 +188,9 @@ config ARCH_HAS_ILOG2_U64 
config ARCH_HAS_BANDGAP

	bool



config FIX_EARLYCON_MEM

	def_bool y if MMU



config GENERIC_HWEIGHT

	bool

	default y
@@ -1496,6 +1499,7 @@ config HOTPLUG_CPU 
config ARM_PSCI

	bool "Support for the ARM Power State Coordination Interface (PSCI)"

	depends on CPU_V7

	select ARM_PSCI_FW

	help

	  Say Y here if you want Linux to communicate with system firmware

	  implementing the PSCI specification for CPU-centric power
@@ -1700,13 +1704,24 @@ config HIGHPTE 
	  consumed by page tables.  Setting this option will allow

	  user-space 2nd level page tables to reside in high memory.



config HW_PERF_EVENTS

	bool "Enable hardware performance counter support for perf events"

	depends on PERF_EVENTS

config CPU_SW_DOMAIN_PAN

	bool "Enable use of CPU domains to implement privileged no-access"

	depends on MMU && !ARM_LPAE

	default y

	help

	  Enable hardware performance counter support for perf events. If

	  disabled, perf events will use software events only.

	  Increase kernel security by ensuring that normal kernel accesses

	  are unable to access userspace addresses.  This can help prevent

	  use-after-free bugs becoming an exploitable privilege escalation

	  by ensuring that magic values (such as LIST_POISON) will always

	  fault when dereferenced.



	  CPUs with low-vector mappings use a best-efforts implementation.

	  Their lower 1MB needs to remain accessible for the vectors, but

	  the remainder of userspace will become appropriately inaccessible.



config HW_PERF_EVENTS

	def_bool y

	depends on ARM_PMU



config SYS_SUPPORTS_HUGETLBFS

       def_bool y

arch/arm/common/mcpm_platsmp.c

+4 −8
Original line number Diff line number Diff line
@@ -65,14 +65,10 @@ static int mcpm_cpu_kill(unsigned int cpu) 
	return !mcpm_wait_for_cpu_powerdown(pcpu, pcluster);

}



static int mcpm_cpu_disable(unsigned int cpu)

static bool mcpm_cpu_can_disable(unsigned int cpu)

{

	/*

	 * We assume all CPUs may be shut down.

	 * This would be the hook to use for eventual Secure

	 * OS migration requests as described in the PSCI spec.

	 */

	return 0;

	/* We assume all CPUs may be shut down. */

	return true;

}



static void mcpm_cpu_die(unsigned int cpu)
@@ -92,7 +88,7 @@ static struct smp_operations __initdata mcpm_smp_ops = { 
	.smp_secondary_init	= mcpm_secondary_init,

#ifdef CONFIG_HOTPLUG_CPU

	.cpu_kill		= mcpm_cpu_kill,

	.cpu_disable		= mcpm_cpu_disable,

	.cpu_can_disable	= mcpm_cpu_can_disable,

	.cpu_die		= mcpm_cpu_die,

#endif

};