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Commit c6bb9cec authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'for-4.4-rc/ti-clk-fixes' of https://github.com/t-kristo/linux-pm into clk-fixes 

Pull TI clock driver fixes from Tero Kristo:

* 'for-4.4-rc/ti-clk-fixes' of https://github.com/t-kristo/linux-pm:
  clk: ti: drop locking code from mux/divider drivers
  clk: ti816x: Add missing dmtimer clkdev entries
  clk: ti: fapll: fix wrong do_div() usage
  clk: ti: clkt_dpll: fix wrong do_div() usage
parents c21ac066 167af5ef

drivers/clk/ti/clk-816x.c

+2 −0
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ static struct ti_dt_clk dm816x_clks[] = { 
	DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),

	DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),

	DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),

	DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),

	DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),

	DT_CLK(NULL, "mpu_ck", "mpu_ck"),

	DT_CLK(NULL, "timer1_fck", "timer1_fck"),

	DT_CLK(NULL, "timer2_fck", "timer2_fck"),

drivers/clk/ti/clkt_dpll.c

+2 −2
Original line number Diff line number Diff line
@@ -240,7 +240,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) 
 */

unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)

{

	long long dpll_clk;

	u64 dpll_clk;

	u32 dpll_mult, dpll_div, v;

	struct dpll_data *dd;
@@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) 
	dpll_div = v & dd->div1_mask;

	dpll_div >>= __ffs(dd->div1_mask);



	dpll_clk = (long long)clk_get_rate(dd->clk_ref) * dpll_mult;

	dpll_clk = (u64)clk_get_rate(dd->clk_ref) * dpll_mult;

	do_div(dpll_clk, dpll_div + 1);



	return dpll_clk;

drivers/clk/ti/divider.c

+3 −13
Original line number Diff line number Diff line
@@ -214,7 +214,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 
{

	struct clk_divider *divider;

	unsigned int div, value;

	unsigned long flags = 0;

	u32 val;



	if (!hw || !rate)
@@ -228,9 +227,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 
	if (value > div_mask(divider))

		value = div_mask(divider);



	if (divider->lock)

		spin_lock_irqsave(divider->lock, flags);



	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {

		val = div_mask(divider) << (divider->shift + 16);

	} else {
@@ -240,9 +236,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 
	val |= value << divider->shift;

	ti_clk_ll_ops->clk_writel(val, divider->reg);



	if (divider->lock)

		spin_unlock_irqrestore(divider->lock, flags);



	return 0;

}
@@ -256,8 +249,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, 
				     const char *parent_name,

				     unsigned long flags, void __iomem *reg,

				     u8 shift, u8 width, u8 clk_divider_flags,

				     const struct clk_div_table *table,

				     spinlock_t *lock)

				     const struct clk_div_table *table)

{

	struct clk_divider *div;

	struct clk *clk;
@@ -288,7 +280,6 @@ static struct clk *_register_divider(struct device *dev, const char *name, 
	div->shift = shift;

	div->width = width;

	div->flags = clk_divider_flags;

	div->lock = lock;

	div->hw.init = &init;

	div->table = table;
@@ -421,7 +412,7 @@ struct clk *ti_clk_register_divider(struct ti_clk *setup) 


	clk = _register_divider(NULL, setup->name, div->parent,

				flags, (void __iomem *)reg, div->bit_shift,

				width, div_flags, table, NULL);

				width, div_flags, table);



	if (IS_ERR(clk))

		kfree(table);
@@ -584,8 +575,7 @@ static void __init of_ti_divider_clk_setup(struct device_node *node) 
		goto cleanup;



	clk = _register_divider(NULL, node->name, parent_name, flags, reg,

				shift, width, clk_divider_flags, table,

				NULL);

				shift, width, clk_divider_flags, table);



	if (!IS_ERR(clk)) {

		of_clk_add_provider(node, of_clk_src_simple_get, clk);

drivers/clk/ti/fapll.c

+2 −2
Original line number Diff line number Diff line
@@ -168,7 +168,7 @@ static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw, 
{

	struct fapll_data *fd = to_fapll(hw);

	u32 fapll_n, fapll_p, v;

	long long rate;

	u64 rate;



	if (ti_fapll_clock_is_bypass(fd))

		return parent_rate;
@@ -314,7 +314,7 @@ static unsigned long ti_fapll_synth_recalc_rate(struct clk_hw *hw, 
{

	struct fapll_synth *synth = to_synth(hw);

	u32 synth_div_m;

	long long rate;

	u64 rate;



	/* The audio_pll_clk1 is hardwired to produce 32.768KiHz clock */

	if (!synth->div)

drivers/clk/ti/mux.c

+3 −12
Original line number Diff line number Diff line
@@ -69,7 +69,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) 
{

	struct clk_mux *mux = to_clk_mux(hw);

	u32 val;

	unsigned long flags = 0;



	if (mux->table) {

		index = mux->table[index];
@@ -81,9 +80,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) 
			index++;

	}



	if (mux->lock)

		spin_lock_irqsave(mux->lock, flags);



	if (mux->flags & CLK_MUX_HIWORD_MASK) {

		val = mux->mask << (mux->shift + 16);

	} else {
@@ -93,9 +89,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) 
	val |= index << mux->shift;

	ti_clk_ll_ops->clk_writel(val, mux->reg);



	if (mux->lock)

		spin_unlock_irqrestore(mux->lock, flags);



	return 0;

}
@@ -109,7 +102,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, 
				 const char **parent_names, u8 num_parents,

				 unsigned long flags, void __iomem *reg,

				 u8 shift, u32 mask, u8 clk_mux_flags,

				 u32 *table, spinlock_t *lock)

				 u32 *table)

{

	struct clk_mux *mux;

	struct clk *clk;
@@ -133,7 +126,6 @@ static struct clk *_register_mux(struct device *dev, const char *name, 
	mux->shift = shift;

	mux->mask = mask;

	mux->flags = clk_mux_flags;

	mux->lock = lock;

	mux->table = table;

	mux->hw.init = &init;
@@ -175,7 +167,7 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup) 


	return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,

			     flags, (void __iomem *)reg, mux->bit_shift, mask,

			     mux_flags, NULL, NULL);

			     mux_flags, NULL);

}



/**
@@ -227,8 +219,7 @@ static void of_mux_clk_setup(struct device_node *node) 
	mask = (1 << fls(mask)) - 1;



	clk = _register_mux(NULL, node->name, parent_names, num_parents,

			    flags, reg, shift, mask, clk_mux_flags, NULL,

			    NULL);

			    flags, reg, shift, mask, clk_mux_flags, NULL);



	if (!IS_ERR(clk))

		of_clk_add_provider(node, of_clk_src_simple_get, clk);