ath9k_hw: define registers/macros to support Antenna diversity

#define AR_PHY_EXT_CCA0         (AR_AGC_BASE + 0x20)

#define AR_PHY_RESTART          (AR_AGC_BASE + 0x24)

/*

 * Antenna Diversity  settings

 */

#define AR_PHY_MC_GAIN_CTRL     (AR_AGC_BASE + 0x28)

#define AR_ANT_DIV_CTRL_ALL	0x7e000000

#define AR_ANT_DIV_CTRL_ALL_S	25

#define AR_ANT_DIV_ENABLE	0x1000000

#define AR_ANT_DIV_ENABLE_S	24

#define AR_PHY_9485_ANT_FAST_DIV_BIAS			0x00007e00

#define AR_PHY_9485_ANT_FAST_DIV_BIAS_S                  9

#define AR_PHY_9485_ANT_DIV_LNADIV			0x01000000

#define AR_PHY_9485_ANT_DIV_LNADIV_S			24

#define AR_PHY_9485_ANT_DIV_ALT_LNACONF			0x06000000

#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S		25

#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF		0x18000000

#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S		27

#define AR_PHY_9485_ANT_DIV_ALT_GAINTB			0x20000000

#define AR_PHY_9485_ANT_DIV_ALT_GAINTB_S		29

#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB			0x40000000

#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S		30

#define AR_PHY_9485_ANT_DIV_LNA1_MINUS_LNA2		0x0

#define AR_PHY_9485_ANT_DIV_LNA2			0x1

#define AR_PHY_9485_ANT_DIV_LNA1			0x2

#define AR_PHY_9485_ANT_DIV_LNA1_PLUS_LNA2		0x3

#define AR_PHY_EXTCHN_PWRTHR1   (AR_AGC_BASE + 0x2c)

#define AR_PHY_EXT_CHN_WIN      (AR_AGC_BASE + 0x30)

#define AR_PHY_20_40_DET_THR    (AR_AGC_BASE + 0x34)

	u8 main_lna_conf;

	u8 alt_lna_conf;

	u8 fast_div_bias;

	u8 main_gaintb;

	u8 alt_gaintb;

	int lna1_lna2_delta;

};

/**