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Commit c619eed4 authored by Eric Anholt's avatar Eric Anholt
Browse files

drm/i915: More s/IS_IRONLAKE/HAS_PCH_SPLIT for Sandybridge. 



I think this is pretty much correct.  Not really tested.

Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent faa7bde6

drivers/gpu/drm/i915/i915_irq.c

+1 −1
Original line number Diff line number Diff line
@@ -166,7 +166,7 @@ void intel_enable_asle (struct drm_device *dev) 
{

	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;



	if (IS_IRONLAKE(dev))

	if (HAS_PCH_SPLIT(dev))

		ironlake_enable_display_irq(dev_priv, DE_GSE);

	else

		i915_enable_pipestat(dev_priv, 1,

drivers/gpu/drm/i915/intel_display.c

+3 −3
Original line number Diff line number Diff line
@@ -886,7 +886,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 
	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {

		int lvds_reg;



		if (IS_IRONLAKE(dev))

		if (HAS_PCH_SPLIT(dev))

			lvds_reg = PCH_LVDS;

		else

			lvds_reg = LVDS;
@@ -3320,12 +3320,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, 
		/* set the dithering flag */

		if (IS_I965G(dev)) {

			if (dev_priv->lvds_dither) {

				if (IS_IRONLAKE(dev))

				if (HAS_PCH_SPLIT(dev))

					pipeconf |= PIPE_ENABLE_DITHER;

				else

					lvds |= LVDS_ENABLE_DITHER;

			} else {

				if (IS_IRONLAKE(dev))

				if (HAS_PCH_SPLIT(dev))

					pipeconf &= ~PIPE_ENABLE_DITHER;

				else

					lvds &= ~LVDS_ENABLE_DITHER;

drivers/gpu/drm/i915/intel_dp.c

+3 −3
Original line number Diff line number Diff line
@@ -231,7 +231,7 @@ intel_dp_aux_ch(struct intel_output *intel_output, 
	 */

	if (IS_eDP(intel_output))

		aux_clock_divider = 225; /* eDP input clock at 450Mhz */

	else if (IS_IRONLAKE(dev))

	else if (HAS_PCH_SPLIT(dev))

		aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */

	else

		aux_clock_divider = intel_hrawclk(dev) / 2;
@@ -584,7 +584,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 
	intel_dp_compute_m_n(3, lane_count,

			     mode->clock, adjusted_mode->clock, &m_n);



	if (IS_IRONLAKE(dev)) {

	if (HAS_PCH_SPLIT(dev)) {

		if (intel_crtc->pipe == 0) {

			I915_WRITE(TRANSA_DATA_M1,

				   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
@@ -1176,7 +1176,7 @@ intel_dp_detect(struct drm_connector *connector) 


	dp_priv->has_audio = false;



	if (IS_IRONLAKE(dev))

	if (HAS_PCH_SPLIT(dev))

		return ironlake_dp_detect(connector);



	temp = I915_READ(PORT_HOTPLUG_EN);

drivers/gpu/drm/i915/intel_hdmi.c

+2 −2
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) 
	/* HW workaround, need to toggle enable bit off and on for 12bpc, but

	 * we do this anyway which shows more stable in testing.

	 */

	if (IS_IRONLAKE(dev)) {

	if (HAS_PCH_SPLIT(dev)) {

		I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE);

		POSTING_READ(hdmi_priv->sdvox_reg);

	}
@@ -99,7 +99,7 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) 
	/* HW workaround, need to write this twice for issue that may result

	 * in first write getting masked.

	 */

	if (IS_IRONLAKE(dev)) {

	if (HAS_PCH_SPLIT(dev)) {

		I915_WRITE(hdmi_priv->sdvox_reg, temp);

		POSTING_READ(hdmi_priv->sdvox_reg);

	}

drivers/gpu/drm/i915/intel_i2c.c

+1 −1
Original line number Diff line number Diff line
@@ -128,7 +128,7 @@ intel_i2c_reset_gmbus(struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (IS_IRONLAKE(dev)) {

	if (HAS_PCH_SPLIT(dev)) {

		I915_WRITE(PCH_GMBUS0, 0);

	} else {

		I915_WRITE(GMBUS0, 0);