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Commit c5c98a58 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Add a comment about WIZ hashing vs. thread counts 



Add a comment next to our WIZ hashing setup to remind people about the
link between WIZ hashing disable bit and PS/WM thread counts.

Suggested-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 36075a4c

drivers/gpu/drm/i915/intel_pm.c

+16 −0
Original line number Diff line number Diff line
@@ -4664,6 +4664,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) 
	/*

	 * BSpec recoomends 8x4 when MSAA is used,

	 * however in practice 16x4 seems fastest.

	 *

	 * Note that PS/WM thread counts depend on the WIZ hashing

	 * disable bit, which we don't touch here, but it's good

	 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).

	 */

	I915_WRITE(GEN6_GT_MODE,

		   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
@@ -4847,6 +4851,10 @@ static void gen8_init_clock_gating(struct drm_device *dev) 
	/*

	 * BSpec recommends 8x4 when MSAA is used,

	 * however in practice 16x4 seems fastest.

	 *

	 * Note that PS/WM thread counts depend on the WIZ hashing

	 * disable bit, which we don't touch here, but it's good

	 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).

	 */

	I915_WRITE(GEN7_GT_MODE,

		   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
@@ -4883,6 +4891,10 @@ static void haswell_init_clock_gating(struct drm_device *dev) 
	/*

	 * BSpec recommends 8x4 when MSAA is used,

	 * however in practice 16x4 seems fastest.

	 *

	 * Note that PS/WM thread counts depend on the WIZ hashing

	 * disable bit, which we don't touch here, but it's good

	 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).

	 */

	I915_WRITE(GEN7_GT_MODE,

		   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
@@ -4971,6 +4983,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
	/*

	 * BSpec recommends 8x4 when MSAA is used,

	 * however in practice 16x4 seems fastest.

	 *

	 * Note that PS/WM thread counts depend on the WIZ hashing

	 * disable bit, which we don't touch here, but it's good

	 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).

	 */

	I915_WRITE(GEN7_GT_MODE,

		   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);