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Commit c5a30f85 authored by Pavel Hofman's avatar Pavel Hofman Committed by Jaroslav Kysela
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[ALSA] ice1724 - Misc fixes for Prodigy192 



- always set 256fs in SPDIF master clock mode
- disable deemphasis filter in AK4114 for Prodigy192

Signed-off-by: default avatarPavel Hofman <dustin@seznam.cz>
Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
Signed-off-by: default avatarJaroslav Kysela <perex@suse.cz>
parent bccad14e

sound/pci/ice1712/ice1724.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -1666,7 +1666,12 @@ static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol, 
	spin_lock_irq(&ice->reg_lock);

	spin_lock_irq(&ice->reg_lock);

	oval = inb(ICEMT1724(ice, RATE));

	oval = inb(ICEMT1724(ice, RATE));

	if (ucontrol->value.enumerated.item[0] == spdif) {

	if (ucontrol->value.enumerated.item[0] == spdif) {

		unsigned char i2s_oval;

		outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));

		outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));

		/* setting 256fs */

		i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));

		outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X,

		     ICEMT1724(ice, I2S_FORMAT));

	} else {

	} else {

		rate = rates[ucontrol->value.integer.value[0] % 15];

		rate = rates[ucontrol->value.integer.value[0] % 15];

		if (rate <= get_max_rate(ice)) {

		if (rate <= get_max_rate(ice)) {

sound/pci/ice1712/prodigy192.c

+11 −1
Original line number Original line Diff line number Diff line
@@ -26,6 +26,13 @@ 
 * 			CCLK (pin 34) -- GPIO9 pin 76

 * 			CCLK (pin 34) -- GPIO9 pin 76

 * 			CSN  (pin 35) -- GPIO8 pin 75

 * 			CSN  (pin 35) -- GPIO8 pin 75

 *   		- output data Mode 7 (24bit, I2S, slave)

 *   		- output data Mode 7 (24bit, I2S, slave)

 *		- both MCKO1 and MCKO2 of ak4114 are fed to FPGA, which

 *		  outputs master clock to SPMCLKIN of ice1724.

 *		  Experimentally I found out that only a combination of

 *		  OCKS0=1, OCKS1=1 (128fs, 64fs output) and ice1724 -

 *		  VT1724_MT_I2S_MCLK_128X=0 (256fs input) yields correct

 *		  sampling rate. That means the the FPGA doubles the

 *		  MCK01 rate.

 *

 *

 *	Copyright (c) 2003 Takashi Iwai <tiwai@suse.de>

 *	Copyright (c) 2003 Takashi Iwai <tiwai@suse.de>

 *      Copyright (c) 2003 Dimitromanolakis Apostolos <apostol@cs.utoronto.ca>

 *      Copyright (c) 2003 Dimitromanolakis Apostolos <apostol@cs.utoronto.ca>
@@ -714,7 +721,10 @@ static int prodigy192_ak4114_init(struct snd_ice1712 *ice) 
{

{

	static const unsigned char ak4114_init_vals[] = {

	static const unsigned char ak4114_init_vals[] = {

		AK4114_RST | AK4114_PWN | AK4114_OCKS0 | AK4114_OCKS1,

		AK4114_RST | AK4114_PWN | AK4114_OCKS0 | AK4114_OCKS1,

		AK4114_DIF_I24I2S, /* ice1724 expects I2S and provides clock */

		/* ice1724 expects I2S and provides clock,

		 * DEM0 disables the deemphasis filter

		 */

		AK4114_DIF_I24I2S | AK4114_DEM0 ,

		AK4114_TX1E,

		AK4114_TX1E,

		AK4114_EFH_1024 | AK4114_DIT, /* default input RX0 */

		AK4114_EFH_1024 | AK4114_DIT, /* default input RX0 */

		0,

		0,