Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c4c17252 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'ntb-3.12' of git://github.com/jonmason/ntb 

Pull NTB (non-transparent bridge) updates from Jon Mason:
 "NTB driver bug fixes to address issues in NTB-RP enablement, spad,
  debugfs, and USD/DSD identification.

  Add a workaround on Xeon NTB devices for b2bdoorbell errata.  Also,
  add new NTB driver features to support 32bit x86, DMA engine support,
  and NTB-RP support.

  Finally, a few clean-ups and update to MAINTAINERS for the NTB git
  tree and wiki location"

* tag 'ntb-3.12' of git://github.com/jonmason/ntb:
  ntb: clean up unnecessary MSI/MSI-X capability find
  MAINTAINERS: Add Website and Git Tree for NTB
  NTB: Update Version
  NTB: Comment Fix
  NTB: Remove unused variable
  NTB: Remove References of non-B2B BWD HW
  NTB: NTB-RP support
  NTB: Rename Variables for NTB-RP
  NTB: Use DMA Engine to Transmit and Receive
  NTB: Enable 32bit Support
  NTB: Update Device IDs
  NTB: BWD Link Recovery
  NTB: Xeon Errata Workaround
  NTB: Correct debugfs to work with more than 1 NTB Device
  NTB: Correct USD/DSD Identification
  NTB: Correct Number of Scratch Pad Registers
  NTB: Add Error Handling in ntb_device_setup
parents 8de4651a 73f47cad

MAINTAINERS

+2 −0
Original line number Diff line number Diff line
@@ -5889,6 +5889,8 @@ F: drivers/scsi/nsp32* 
NTB DRIVER

M:	Jon Mason <jon.mason@intel.com>

S:	Supported

W:	https://github.com/jonmason/ntb/wiki

T:	git git://github.com/jonmason/ntb.git

F:	drivers/ntb/

F:	drivers/net/ntb_netdev.c

F:	include/linux/ntb.h

drivers/ntb/Kconfig

+1 −1
Original line number Diff line number Diff line 
config NTB

       tristate "Intel Non-Transparent Bridge support"

       depends on PCI

       depends on X86_64

       depends on X86

       help

        The PCI-E Non-transparent bridge hardware is a point-to-point PCI-E bus

        connecting 2 systems.  When configured, writes to the device's PCI

drivers/ntb/ntb_hw.c

+399 −102

File changed.

Preview size limit exceeded, changes collapsed.

drivers/ntb/ntb_hw.h

+87 −18
Original line number Diff line number Diff line
@@ -47,16 +47,36 @@ 
 */



#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF		0x3725

#define PCI_DEVICE_ID_INTEL_NTB_CLASSIC_JSF	0x3726

#define PCI_DEVICE_ID_INTEL_NTB_RP_JSF		0x3727

#define PCI_DEVICE_ID_INTEL_NTB_RP_SNB		0x3C08

#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF		0x3726

#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF		0x3727

#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB		0x3C0D

#define PCI_DEVICE_ID_INTEL_NTB_CLASSIC_SNB	0x3C0E

#define PCI_DEVICE_ID_INTEL_NTB_2ND_SNB		0x3C0F

#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB		0x3C0E

#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB		0x3C0F

#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT		0x0E0D

#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT		0x0E0E

#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT		0x0E0F

#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX		0x2F0D

#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX		0x2F0E

#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX		0x2F0F

#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD		0x0C4E



#define msix_table_size(control)	((control & PCI_MSIX_FLAGS_QSIZE)+1)



#ifndef readq

static inline u64 readq(void __iomem *addr)

{

	return readl(addr) | (((u64) readl(addr + 4)) << 32LL);

}

#endif



#ifndef writeq

static inline void writeq(u64 val, void __iomem *addr)

{

	writel(val & 0xffffffff, addr);

	writel(val >> 32, addr + 4);

}

#endif



#define NTB_BAR_MMIO		0

#define NTB_BAR_23		2

#define NTB_BAR_45		4
@@ -68,7 +88,7 @@ 


#define NTB_HB_TIMEOUT		msecs_to_jiffies(1000)



#define NTB_NUM_MW		2

#define NTB_MAX_NUM_MW		2



enum ntb_hw_event {

	NTB_EVENT_SW_EVENT0 = 0,
@@ -96,18 +116,19 @@ struct ntb_device { 
	struct pci_dev *pdev;

	struct msix_entry *msix_entries;

	void __iomem *reg_base;

	struct ntb_mw mw[NTB_NUM_MW];

	struct ntb_mw mw[NTB_MAX_NUM_MW];

	struct {

		unsigned int max_spads;

		unsigned int max_db_bits;

		unsigned int msix_cnt;

		unsigned char max_mw;

		unsigned char max_spads;

		unsigned char max_db_bits;

		unsigned char msix_cnt;

	} limits;

	struct {

		void __iomem *pdb;

		void __iomem *pdb_mask;

		void __iomem *sdb;

		void __iomem *sbar2_xlat;

		void __iomem *sbar4_xlat;

		void __iomem *ldb;

		void __iomem *ldb_mask;

		void __iomem *rdb;

		void __iomem *bar2_xlat;

		void __iomem *bar4_xlat;

		void __iomem *spad_write;

		void __iomem *spad_read;

		void __iomem *lnk_cntl;
@@ -124,11 +145,44 @@ struct ntb_device { 
	unsigned char num_msix;

	unsigned char bits_per_vector;

	unsigned char max_cbs;

	unsigned char link_width;

	unsigned char link_speed;

	unsigned char link_status;



	struct delayed_work hb_timer;

	unsigned long last_ts;



	struct delayed_work lr_timer;



	struct dentry *debugfs_dir;

};



/**

 * ntb_max_cbs() - return the max callbacks

 * @ndev: pointer to ntb_device instance

 *

 * Given the ntb pointer, return the maximum number of callbacks

 *

 * RETURNS: the maximum number of callbacks

 */

static inline unsigned char ntb_max_cbs(struct ntb_device *ndev)

{

	return ndev->max_cbs;

}



/**

 * ntb_max_mw() - return the max number of memory windows

 * @ndev: pointer to ntb_device instance

 *

 * Given the ntb pointer, return the maximum number of memory windows

 *

 * RETURNS: the maximum number of memory windows

 */

static inline unsigned char ntb_max_mw(struct ntb_device *ndev)

{

	return ndev->limits.max_mw;

}



/**

 * ntb_hw_link_status() - return the hardware link status

 * @ndev: pointer to ntb_device instance
@@ -146,7 +200,7 @@ static inline bool ntb_hw_link_status(struct ntb_device *ndev) 
 * ntb_query_pdev() - return the pci_dev pointer

 * @ndev: pointer to ntb_device instance

 *

 * Given the ntb pointer return the pci_dev pointerfor the NTB hardware device

 * Given the ntb pointer, return the pci_dev pointer for the NTB hardware device

 *

 * RETURNS: a pointer to the ntb pci_dev

 */
@@ -155,6 +209,20 @@ static inline struct pci_dev *ntb_query_pdev(struct ntb_device *ndev) 
	return ndev->pdev;

}



/**

 * ntb_query_debugfs() - return the debugfs pointer

 * @ndev: pointer to ntb_device instance

 *

 * Given the ntb pointer, return the debugfs directory pointer for the NTB

 * hardware device

 *

 * RETURNS: a pointer to the debugfs directory

 */

static inline struct dentry *ntb_query_debugfs(struct ntb_device *ndev)

{

	return ndev->debugfs_dir;

}



struct ntb_device *ntb_register_transport(struct pci_dev *pdev,

					  void *transport);

void ntb_unregister_transport(struct ntb_device *ndev);
@@ -172,9 +240,10 @@ int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val); 
int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val);

int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val);

int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val);

resource_size_t ntb_get_mw_base(struct ntb_device *ndev, unsigned int mw);

void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw);

resource_size_t ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw);

void ntb_ring_sdb(struct ntb_device *ndev, unsigned int idx);

u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw);

void ntb_ring_doorbell(struct ntb_device *ndev, unsigned int idx);

void *ntb_find_transport(struct pci_dev *pdev);



int ntb_transport_init(struct pci_dev *pdev);

drivers/ntb/ntb_regs.h

+35 −15
Original line number Diff line number Diff line
@@ -46,23 +46,24 @@ 
 * Jon Mason <jon.mason@intel.com>

 */



#define NTB_LINK_ENABLE		0x0000

#define NTB_LINK_DISABLE	0x0002

#define NTB_LINK_STATUS_ACTIVE	0x2000

#define NTB_LINK_SPEED_MASK	0x000f

#define NTB_LINK_WIDTH_MASK	0x03f0



#define SNB_MSIX_CNT		4

#define SNB_MAX_SPADS		16

#define SNB_MAX_COMPAT_SPADS	8

#define SNB_MAX_B2B_SPADS	16

#define SNB_MAX_COMPAT_SPADS	16

/* Reserve the uppermost bit for link interrupt */

#define SNB_MAX_DB_BITS		15

#define SNB_DB_BITS_PER_VEC	5

#define SNB_MAX_MW		2

#define SNB_ERRATA_MAX_MW	1



#define SNB_DB_HW_LINK		0x8000



#define SNB_PCICMD_OFFSET	0x0504

#define SNB_DEVCTRL_OFFSET	0x0598

#define SNB_SLINK_STATUS_OFFSET	0x05A2

#define SNB_LINK_STATUS_OFFSET	0x01A2



#define SNB_PBAR2LMT_OFFSET	0x0000
@@ -74,6 +75,9 @@ 
#define SNB_SBAR2XLAT_OFFSET	0x0030

#define SNB_SBAR4XLAT_OFFSET	0x0038

#define SNB_SBAR0BASE_OFFSET	0x0040

#define SNB_SBAR0BASE_OFFSET	0x0040

#define SNB_SBAR2BASE_OFFSET	0x0048

#define SNB_SBAR4BASE_OFFSET	0x0050

#define SNB_SBAR2BASE_OFFSET	0x0048

#define SNB_SBAR4BASE_OFFSET	0x0050

#define SNB_NTBCNTL_OFFSET	0x0058
@@ -88,19 +92,28 @@ 
#define SNB_WCCNTRL_OFFSET	0x00e0

#define SNB_B2B_SPAD_OFFSET	0x0100

#define SNB_B2B_DOORBELL_OFFSET	0x0140

#define SNB_B2B_XLAT_OFFSET	0x0144

#define SNB_B2B_XLAT_OFFSETL	0x0144

#define SNB_B2B_XLAT_OFFSETU	0x0148



#define SNB_MBAR01_USD_ADDR	0x000000210000000CULL

#define SNB_MBAR23_USD_ADDR	0x000000410000000CULL

#define SNB_MBAR45_USD_ADDR	0x000000810000000CULL

#define SNB_MBAR01_DSD_ADDR	0x000000200000000CULL

#define SNB_MBAR23_DSD_ADDR	0x000000400000000CULL

#define SNB_MBAR45_DSD_ADDR	0x000000800000000CULL



#define BWD_MSIX_CNT		34

#define BWD_MAX_SPADS		16

#define BWD_MAX_COMPAT_SPADS	16

#define BWD_MAX_DB_BITS		34

#define BWD_DB_BITS_PER_VEC	1

#define BWD_MAX_MW		2



#define BWD_PCICMD_OFFSET	0xb004

#define BWD_MBAR23_OFFSET	0xb018

#define BWD_MBAR45_OFFSET	0xb020

#define BWD_DEVCTRL_OFFSET	0xb048

#define BWD_LINK_STATUS_OFFSET	0xb052

#define BWD_ERRCORSTS_OFFSET	0xb110



#define BWD_SBAR2XLAT_OFFSET	0x0008

#define BWD_SBAR4XLAT_OFFSET	0x0010
@@ -118,6 +131,22 @@ 
#define BWD_B2B_SPADSEMA_OFFSET	0x80c0

#define BWD_B2B_STKYSPAD_OFFSET	0x80c4



#define BWD_MODPHY_PCSREG4	0x1c004

#define BWD_MODPHY_PCSREG6	0x1c006



#define BWD_IP_BASE		0xC000

#define BWD_DESKEWSTS_OFFSET	(BWD_IP_BASE + 0x3024)

#define BWD_LTSSMERRSTS0_OFFSET (BWD_IP_BASE + 0x3180)

#define BWD_LTSSMSTATEJMP_OFFSET	(BWD_IP_BASE + 0x3040)

#define BWD_IBSTERRRCRVSTS0_OFFSET	(BWD_IP_BASE + 0x3324)



#define BWD_DESKEWSTS_DBERR	(1 << 15)

#define BWD_LTSSMERRSTS0_UNEXPECTEDEI	(1 << 20)

#define BWD_LTSSMSTATEJMP_FORCEDETECT	(1 << 2)

#define BWD_IBIST_ERR_OFLOW	0x7FFF7FFF



#define NTB_CNTL_CFG_LOCK	(1 << 0)

#define NTB_CNTL_LINK_DISABLE	(1 << 1)

#define NTB_CNTL_BAR23_SNOOP	(1 << 2)

#define NTB_CNTL_BAR45_SNOOP	(1 << 6)

#define BWD_CNTL_LINK_DOWN	(1 << 16)
@@ -128,12 +157,3 @@ 
#define BWD_PPD_INIT_LINK	0x0008

#define BWD_PPD_CONN_TYPE	0x0300

#define BWD_PPD_DEV_TYPE	0x1000
 


#define BWD_PBAR2XLAT_USD_ADDR	0x0000004000000000

#define BWD_PBAR4XLAT_USD_ADDR	0x0000008000000000

#define BWD_MBAR23_USD_ADDR	0x000000410000000C

#define BWD_MBAR45_USD_ADDR	0x000000810000000C

#define BWD_PBAR2XLAT_DSD_ADDR	0x0000004100000000

#define BWD_PBAR4XLAT_DSD_ADDR	0x0000008100000000

#define BWD_MBAR23_DSD_ADDR	0x000000400000000C

#define BWD_MBAR45_DSD_ADDR	0x000000800000000C