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Commit c478b581 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
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powerpc/powermac: Fix occasional SMP boot failure



The PowerMac kernel occasionally fails to bring up the secondary CPUs on
SMP, the trigger factor seem to be fairly random and related to location
of code and data.

This appears to be due to the initial loading of the TOC value by the
secondary processor which now happens before we clear HID4:RM_CI (Real
Mode Cache Invalidate). This bit should really be cleared before we do
any load or store other than fetching code.

This fix works based on the assumption that all SMP 64-bit PowerMacs use
variants of the 970, which fortunately is true, by explicitely clearing
that bit, adding an slbia for good measure as RM_CI mode is known to
create bogus ERAT entries.

I also removed some spurrious debug output that was left enabled by
mistake while at it.

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent fc7a9feb
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+9 −0
Original line number Diff line number Diff line
@@ -1518,6 +1518,15 @@ _GLOBAL(pmac_secondary_start)
	/* turn on 64-bit mode */
	bl	.enable_64b_mode

	li	r0,0
	mfspr	r3,SPRN_HID4
	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
	sync
	mtspr	SPRN_HID4,r3
	isync
	sync
	slbia

	/* get TOC pointer (real address) */
	bl	.relative_toc

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@
#include <asm/pmac_low_i2c.h>
#include <asm/pmac_pfunc.h>

#define DEBUG
#undef DEBUG

#ifdef DEBUG
#define DBG(fmt...) udbg_printf(fmt)