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Commit c424cb24 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
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[TG3]: Add phy workaround 



Add some PHY workaround code to reduce jitter on some PHYs.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c8e1e82b

drivers/net/tg3.c

+13 −4
Original line number Diff line number Diff line
@@ -1030,6 +1030,12 @@ static int tg3_phy_reset(struct tg3 *tp) 
		tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);

		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);

	}

	else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {

		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);

		tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);

		tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);

		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);

	}

	/* Set Extended packet length bit (bit 14) on all chips that */

	/* support jumbo frames */

	if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
@@ -10360,10 +10366,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)

		tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;



	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&

	    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&

	    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787))

	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {

		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||

		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)

			tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;

		else

			tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;

	}



	tp->coalesce_mode = 0;

	if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&

drivers/net/tg3.h

+1 −0
Original line number Diff line number Diff line
@@ -2215,6 +2215,7 @@ struct tg3 { 
#define TG3_FLG2_HW_TSO_2		0x08000000

#define TG3_FLG2_HW_TSO			(TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)

#define TG3_FLG2_1SHOT_MSI		0x10000000

#define TG3_FLG2_PHY_JITTER_BUG		0x20000000



	u32				split_mode_max_reqs;

#define SPLIT_MODE_5704_MAX_REQ		3