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Commit c40b92e0 authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] Ocelot 3: Fix build errors after the recent move of Marvell headers. 



Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 088cf96a

arch/mips/momentum/ocelot_3/setup.c

+12 −12
Original line number Diff line number Diff line
@@ -329,22 +329,22 @@ void __init plat_setup(void) 
	/* shut down ethernet ports, just to be sure our memory doesn't get

	 * corrupted by random ethernet traffic.

	 */

	MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);

	MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);

	MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);

	MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);

	MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);

	MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);

	MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);

	MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);

	do {}

	  while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);

	  while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);

	do {}

	  while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);

	  while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);

	do {}

	  while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);

	  while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);

	do {}

	  while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);

	MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),

		 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);

	MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),

		 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);

	  while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);

	MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),

		 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);

	MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),

		 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);



	/* Turn off the Bit-Error LED */

	OCELOT_FPGA_WRITE(0x80, CLR);